702 lines
26 KiB
C#
702 lines
26 KiB
C#
// <copyright file="Disassembler.cs" company="Adrian Conlon">
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// Copyright (c) Adrian Conlon. All rights reserved.
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// </copyright>
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namespace EightBit.GameBoy
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{
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public enum IoRegister
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{
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Abbreviated, // FF00 + dd
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Absolute, // FFdd
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Register, // C
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Unused, // Unused!
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}
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public class Disassembler
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{
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private bool prefixCB = false;
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public Disassembler(Bus bus) => this.Bus = bus;
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public Bus Bus { get; }
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public static string AsFlag(byte value, byte flag, string represents) => (value & flag) != 0 ? represents : "-";
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public static string AsFlag(byte value, StatusBits flag, string represents) => AsFlag(value, (byte)flag, represents);
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public static string AsFlag(byte value, Bits flag, string represents) => AsFlag(value, (byte)flag, represents);
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public static string AsFlags(byte value) =>
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$"{AsFlag(value, StatusBits.ZF, "Z")}"
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+ $"{AsFlag(value, StatusBits.NF, "N")}"
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+ $"{AsFlag(value, StatusBits.HC, "H")}"
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+ $"{AsFlag(value, StatusBits.CF, "C")}"
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+ $"{AsFlag(value, Bits.Bit3, "+")}"
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+ $"{AsFlag(value, Bits.Bit2, "+")}"
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+ $"{AsFlag(value, Bits.Bit1, "+")}"
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+ $"{AsFlag(value, Bits.Bit0, "+")}";
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public static string State(LR35902 cpu)
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{
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var pc = cpu.PC;
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var sp = cpu.SP;
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var a = cpu.A;
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var f = cpu.F;
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var b = cpu.B;
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var c = cpu.C;
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var d = cpu.D;
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var e = cpu.E;
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var h = cpu.H;
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var l = cpu.L;
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return
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$"PC={pc.Word:x4} SP={sp.Word:x4} "
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+ $"A={a:x2} F={AsFlags(f)} "
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+ $"B={b:x2} C={c:x2} "
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+ $"D={d:x2} E={e:x2} "
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+ $"H={h:x2} L={l:x2}";
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}
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public string Disassemble(LR35902 cpu)
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{
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this.prefixCB = false;
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return this.Disassemble(cpu, cpu.PC.Word);
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}
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private static string RP(int rp)
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{
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switch (rp)
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{
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case 0:
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return "BC";
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case 1:
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return "DE";
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case 2:
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return "HL";
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case 3:
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return "SP";
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}
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throw new System.ArgumentOutOfRangeException(nameof(rp));
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}
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private static string RP2(int rp)
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{
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switch (rp)
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{
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case 0:
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return "BC";
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case 1:
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return "DE";
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case 2:
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return "HL";
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case 3:
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return "AF";
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}
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throw new System.ArgumentOutOfRangeException(nameof(rp));
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}
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private static string R(int r)
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{
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switch (r)
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{
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case 0:
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return "B";
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case 1:
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return "C";
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case 2:
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return "D";
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case 3:
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return "E";
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case 4:
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return "H";
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case 5:
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return "L";
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case 6:
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return "(HL)";
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case 7:
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return "A";
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}
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throw new System.ArgumentOutOfRangeException(nameof(r));
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}
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private static string IO(byte value)
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{
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switch (value)
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{
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// Port/Mode Registers
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case IoRegisters.P1:
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return "P1";
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case IoRegisters.SB:
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return "SB";
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case IoRegisters.SC:
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return "SC";
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case IoRegisters.DIV:
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return "DIV";
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case IoRegisters.TIMA:
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return "TIMA";
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case IoRegisters.TMA:
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return "TMA";
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case IoRegisters.TAC:
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return "TAC";
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// Interrupt Flags
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case IoRegisters.IF:
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return "IF";
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case IoRegisters.IE:
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return "IE";
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// LCD Display Registers
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case IoRegisters.LCDC:
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return "LCDC";
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case IoRegisters.STAT:
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return "STAT";
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case IoRegisters.SCY:
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return "SCY";
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case IoRegisters.SCX:
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return "SCX";
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case IoRegisters.LY:
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return "LY";
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case IoRegisters.LYC:
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return "LYC";
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case IoRegisters.DMA:
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return "DMA";
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case IoRegisters.BGP:
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return "BGP";
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case IoRegisters.OBP0:
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return "OBP0";
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case IoRegisters.OBP1:
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return "OBP1";
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case IoRegisters.WY:
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return "WY";
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case IoRegisters.WX:
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return "WX";
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// Sound Registers
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case IoRegisters.NR10:
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return "NR10";
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case IoRegisters.NR11:
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return "NR11";
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case IoRegisters.NR12:
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return "NR12";
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case IoRegisters.NR13:
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return "NR13";
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case IoRegisters.NR14:
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return "NR14";
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case IoRegisters.NR21:
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return "NR21";
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case IoRegisters.NR22:
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return "NR22";
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case IoRegisters.NR23:
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return "NR23";
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case IoRegisters.NR24:
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return "NR24";
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case IoRegisters.NR30:
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return "NR30";
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case IoRegisters.NR31:
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return "NR31";
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case IoRegisters.NR32:
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return "NR32";
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case IoRegisters.NR33:
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return "NR33";
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case IoRegisters.NR34:
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return "NR34";
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case IoRegisters.NR41:
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return "NR41";
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case IoRegisters.NR42:
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return "NR42";
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case IoRegisters.NR43:
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return "NR43";
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case IoRegisters.NR44:
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return "NR44";
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case IoRegisters.NR50:
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return "NR50";
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case IoRegisters.NR51:
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return "NR51";
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case IoRegisters.NR52:
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return "NR52";
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case IoRegisters.WAVE_PATTERN_RAM_START:
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return "WAVE_PATTERN_RAM_START";
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case IoRegisters.WAVE_PATTERN_RAM_END:
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return "WAVE_PATTERN_RAM_END";
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// Boot rom control
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case IoRegisters.BOOT_DISABLE:
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return "BOOT_DISABLE";
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default:
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return $"{value:x2}";
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}
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}
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private static string CC(int flag)
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{
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switch (flag)
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{
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case 0:
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return "NZ";
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case 1:
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return "Z";
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case 2:
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return "NC";
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case 3:
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return "C";
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case 4:
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return "PO";
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case 5:
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return "PE";
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case 6:
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return "P";
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case 7:
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return "M";
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}
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throw new System.ArgumentOutOfRangeException(nameof(flag));
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}
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private static string ALU(int which)
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{
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switch (which)
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{
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case 0: // ADD A,n
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return "ADD";
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case 1: // ADC
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return "ADC";
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case 2: // SUB n
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return "SUB";
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case 3: // SBC A,n
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return "SBC";
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case 4: // AND n
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return "AND";
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case 5: // XOR n
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return "XOR";
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case 6: // OR n
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return "OR";
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case 7: // CP n
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return "CP";
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}
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throw new System.ArgumentOutOfRangeException(nameof(which));
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}
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private static string DisassembleCB(ref string specification, int x, int y, int z)
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{
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var output = string.Empty;
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switch (x)
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{
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case 0: // rot[y] r[z]
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switch (y)
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{
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case 0:
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specification = $"RLC {R(z)}";
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break;
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case 1:
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specification = $"RRC {R(z)}";
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break;
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case 2:
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specification = $"RL {R(z)}";
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break;
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case 3:
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specification = $"RR {R(z)}";
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break;
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case 4:
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specification = $"SLA {R(z)}";
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break;
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case 5:
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specification = $"SRA {R(z)}";
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break;
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case 6:
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specification = $"SWAP {R(z)}";
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break;
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case 7:
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specification = $"SRL {R(z)}";
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break;
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}
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break;
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case 1: // BIT y, r[z]
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specification = $"BIT {y},{R(z)}";
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break;
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case 2: // RES y, r[z]
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specification = $"RES {y},{R(z)}";
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break;
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case 3: // SET y, r[z]
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specification = $"SET {y},{R(z)}";
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break;
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}
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return output;
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}
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private string Disassemble(LR35902 cpu, ushort pc)
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{
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var opCode = this.Bus.Peek(pc);
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var decoded = cpu.GetDecodedOpCode(opCode);
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var x = decoded.X;
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var y = decoded.Y;
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var z = decoded.Z;
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var p = decoded.P;
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var q = decoded.Q;
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var immediate = this.Bus.Peek((ushort)(pc + 1));
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var absolute = cpu.PeekWord((ushort)(pc + 1)).Word;
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var displacement = (sbyte)immediate;
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var relative = pc + displacement + 2;
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var indexedImmediate = this.Bus.Peek((ushort)(pc + 1));
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var dumpCount = 0;
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var ioRegister = IoRegister.Unused;
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var output = $"{opCode:x2}";
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var specification = string.Empty;
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if (this.prefixCB)
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{
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output += DisassembleCB(ref specification, x, y, z);
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}
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else
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{
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output += this.DisassembleOther(cpu, pc, ref specification, ref dumpCount, ref ioRegister, x, y, z, p, q);
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}
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for (var i = 0; i < dumpCount; ++i)
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{
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output += $"{this.Bus.Peek((ushort)(pc + i + 1)):x2}";
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}
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output += '\t';
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output += string.Format(specification, (int)immediate, (int)absolute, relative, (int)displacement, indexedImmediate);
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switch (ioRegister)
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{
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case IoRegister.Abbreviated:
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output += $"; register {IO(immediate)}";
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break;
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case IoRegister.Absolute:
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output += "; register (Absolute)";
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break;
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case IoRegister.Register:
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output += $"; register C:{IO(cpu.C)}";
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break;
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case IoRegister.Unused:
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break;
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}
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return output;
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}
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private string DisassembleOther(LR35902 cpu, ushort pc, ref string specification, ref int dumpCount, ref IoRegister ioRegister, int x, int y, int z, int p, int q)
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{
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var output = string.Empty;
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switch (x)
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{
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case 0:
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switch (z)
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{
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case 0: // Relative jumps and assorted ops
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switch (y)
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{
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case 0: // NOP
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specification = "NOP";
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break;
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case 1: // GB: LD (nn),SP
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specification = "LD ({1:X4}H),SP";
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dumpCount += 2;
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break;
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case 2: // GB: STOP
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specification = "STOP";
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break;
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case 3: // JR d
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specification = "JR {2:X4}H";
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dumpCount++;
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break;
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default: // JR cc,d
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specification = $"JR {CC(y - 4)}" + ",{2:X4}H";
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dumpCount++;
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break;
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}
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break;
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case 1: // 16-bit load immediate/add
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switch (q)
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{
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case 0: // LD rp,nn
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specification = $"LD {RP(p)}," + "{1:X4}H";
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dumpCount += 2;
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break;
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case 1: // ADD HL,rp
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specification = $"ADD HL,{RP(p)}";
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break;
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}
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break;
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case 2: // Indirect loading
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switch (q)
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{
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case 0:
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switch (p)
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{
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case 0: // LD (BC),A
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specification = "LD (BC),A";
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break;
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case 1: // LD (DE),A
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specification = "LD (DE),A";
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break;
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case 2: // GB: LDI (HL),A
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specification = "LDI (HL),A";
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break;
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case 3: // GB: LDD (HL),A
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specification = "LDD (HL),A";
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break;
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}
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break;
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case 1:
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switch (p)
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{
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case 0: // LD A,(BC)
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specification = "LD A,(BC)";
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break;
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case 1: // LD A,(DE)
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specification = "LD A,(DE)";
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break;
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case 2: // GB: LDI A,(HL)
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specification = "LDI A,(HL)";
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break;
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case 3: // GB: LDD A,(HL)
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specification = "LDD A,(HL)";
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break;
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}
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break;
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}
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break;
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case 3: // 16-bit INC/DEC
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switch (q)
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{
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case 0: // INC rp
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specification = $"INC {RP(p)}";
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break;
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case 1: // DEC rp
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specification = $"DEC {RP(p)}";
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break;
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}
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break;
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case 4: // 8-bit INC
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specification = $"INC {R(y)}";
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break;
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case 5: // 8-bit DEC
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specification = $"DEC {R(y)}";
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break;
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case 6: // 8-bit load immediate
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specification = $"LD {R(y)}," + "{0:X2}H";
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dumpCount++;
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break;
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case 7: // Assorted operations on accumulator/flags
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switch (y)
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{
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case 0:
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specification = "RLCA";
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break;
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case 1:
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specification = "RRCA";
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break;
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case 2:
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specification = "RLA";
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break;
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case 3:
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specification = "RRA";
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break;
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case 4:
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specification = "DAA";
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break;
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case 5:
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specification = "CPL";
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break;
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case 6:
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specification = "SCF";
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break;
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case 7:
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specification = "CCF";
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break;
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}
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break;
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}
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break;
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case 1: // 8-bit loading
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if (z == 6 && y == 6)
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{
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specification = "HALT"; // Exception (replaces LD (HL), (HL))
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}
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else
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{
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specification = $"LD {R(y)},{R(z)}";
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}
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break;
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case 2: // Operate on accumulator and register/memory location
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specification = $"{ALU(y)} A,{R(z)}";
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break;
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case 3:
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switch (z)
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{
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case 0: // Conditional return
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switch (y)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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specification = $"RET {CC(y)}";
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break;
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case 4:
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specification = "LD (FF00H+{0:X2}H),A";
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ioRegister = IoRegister.Abbreviated;
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dumpCount++;
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break;
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case 5:
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specification = "ADD SP,{4:X4}H";
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dumpCount++;
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break;
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case 6:
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specification = "LD A,(FF00H+{0:X2}H)";
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ioRegister = IoRegister.Abbreviated;
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dumpCount++;
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break;
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case 7:
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specification = "LD HL,SP+{4}";
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dumpCount++;
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break;
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}
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break;
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case 1: // POP & various ops
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switch (q)
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{
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case 0: // POP rp2[p]
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specification = $"POP {RP2(p)}";
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break;
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case 1:
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switch (p)
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{
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case 0: // RET
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specification = "RET";
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break;
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case 1: // GB: RETI
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specification = "RETI";
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break;
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case 2: // JP (HL)
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specification = "JP (HL)";
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break;
|
|
case 3: // LD SP,HL
|
|
specification = "LD SP,HL";
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 2: // Conditional jump
|
|
switch (y)
|
|
{
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
specification = $"JP {CC(y)}" + ",{1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 4:
|
|
specification = "LD (FF00H+C),A";
|
|
ioRegister = IoRegister.Register;
|
|
break;
|
|
case 5:
|
|
specification = "LD ({1:X4}H),A";
|
|
dumpCount += 2;
|
|
break;
|
|
case 6:
|
|
specification = "LD A,(FF00H+C)";
|
|
ioRegister = IoRegister.Register;
|
|
break;
|
|
case 7:
|
|
specification = "LD A,({1:X4}H)";
|
|
dumpCount += 2;
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 3: // Assorted operations
|
|
switch (y)
|
|
{
|
|
case 0: // JP nn
|
|
specification = "JP {1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 1: // CB prefix
|
|
this.prefixCB = true;
|
|
output += this.Disassemble(cpu, ++pc);
|
|
break;
|
|
case 6: // DI
|
|
specification = "DI";
|
|
break;
|
|
case 7: // EI
|
|
specification = "EI";
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 4: // Conditional call: CALL cc[y], nn
|
|
specification = $"CALL {CC(y)}" + ",{1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
case 5: // PUSH & various ops
|
|
switch (q)
|
|
{
|
|
case 0: // PUSH rp2[p]
|
|
specification = $"PUSH {RP2(p)}";
|
|
break;
|
|
case 1:
|
|
switch (p)
|
|
{
|
|
case 0: // CALL nn
|
|
specification = "CALL {1:X4}H";
|
|
dumpCount += 2;
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
break;
|
|
case 6: // Operate on accumulator and immediate operand: alu[y] n
|
|
specification = ALU(y) + " A,{0:X2}H";
|
|
dumpCount++;
|
|
break;
|
|
case 7: // Restart: RST y * 8
|
|
specification = $"RST {y * 8:X2}";
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
return output;
|
|
}
|
|
}
|
|
}
|