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Generate zero-page code for and, or, and xor, when possible.
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@ -1,6 +1,12 @@
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History of SixtyPical
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=====================
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0.16
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----
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* `or a, z`, `and a, z`, and `eor a, z` compile to zero-page operations
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if the address of z < 256.
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0.15
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----
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@ -89,6 +89,5 @@ are trashed inside the block.
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* Automatic tail-call optimization (could be tricky, w/constraints?)
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* Possibly `ld x, [ptr] + y`, possibly `st x, [ptr] + y`.
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* Maybe even `copy [ptra] + y, [ptrb] + y`, which can be compiled to indirect LDA then indirect STA!
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* Optimize `or|and|eor a, z` to zero-page operations if address of z < 256.
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[VICE]: http://vice-emu.sourceforge.net/
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@ -332,7 +332,7 @@ class Compiler(object):
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if isinstance(src, ConstantRef):
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self.emitter.emit(cls(Immediate(Byte(src.value))))
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else:
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self.emitter.emit(cls(Absolute(self.get_label(src.name))))
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self.emitter.emit(cls(self.absolute_or_zero_page(self.get_label(src.name))))
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else:
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raise UnsupportedOpcodeError(instr)
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elif opcode in ('shl', 'shr'):
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@ -133,6 +133,7 @@ class AND(Instruction):
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Absolute: 0x2d,
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AbsoluteX: 0x3d,
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AbsoluteY: 0x39,
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ZeroPage: 0x25,
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}
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@ -231,6 +232,7 @@ class EOR(Instruction):
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Absolute: 0x4d,
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AbsoluteX: 0x5d,
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AbsoluteY: 0x59,
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ZeroPage: 0x45,
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}
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@ -299,6 +301,7 @@ class ORA(Instruction):
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Absolute: 0x0d,
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AbsoluteX: 0x1d,
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AbsoluteY: 0x19,
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ZeroPage: 0x05,
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}
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@ -112,7 +112,8 @@ Memory location with explicit address.
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= $080F STA $0400
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= $0812 RTS
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Accesses to memory locations in zero-page with `ld` and `st` use zero-page addressing.
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Accesses to memory locations in zero-page with `ld` and `st`
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and `and`, `or`, and `xor` use zero-page addressing.
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| byte zp @ $00
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| byte screen @ 100
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@ -126,12 +127,18 @@ Accesses to memory locations in zero-page with `ld` and `st` use zero-page addre
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| st a, screen
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| ld a, zp
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| st a, zp
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| and a, zp
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| or a, zp
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| xor a, zp
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| }
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= $080D LDA $64
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= $080F STA $64
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= $0811 LDA $00
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= $0813 STA $00
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= $0815 RTS
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= $0815 AND $00
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= $0817 ORA $00
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= $0819 EOR $00
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= $081B RTS
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Memory location with initial value.
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