2015-11-14 12:15:29 +00:00
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/*****************************************************************************/
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/* */
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/* gamate.h */
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/* */
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/* Gamate system specific definitions */
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/* */
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/* */
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/* */
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2015-11-29 00:24:01 +00:00
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/* (w) 2015 Groepaz/Hitmen (groepaz@gmx.net) */
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2015-11-29 00:14:59 +00:00
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/* based on technical reference by PeT (mess@utanet.at) */
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2015-11-14 12:15:29 +00:00
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/* */
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/* This software is provided 'as-is', without any expressed or implied */
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/* warranty. In no event will the authors be held liable for any damages */
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/* arising from the use of this software. */
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/* */
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/* Permission is granted to anyone to use this software for any purpose, */
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/* including commercial applications, and to alter it and redistribute it */
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/* freely, subject to the following restrictions: */
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/* */
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/* 1. The origin of this software must not be misrepresented; you must not */
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/* claim that you wrote the original software. If you use this software */
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/* in a product, an acknowledgment in the product documentation would be */
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/* appreciated but is not required. */
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/* 2. Altered source versions must be plainly marked as such, and must not */
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/* be misrepresented as being the original software. */
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/* 3. This notice may not be removed or altered from any source */
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/* distribution. */
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/* */
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/*****************************************************************************/
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#ifndef _GAMATE_H
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#define _GAMATE_H
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/* Check for errors */
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#if !defined(__GAMATE__)
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# error This module may only be used when compiling for the Gamate!
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#endif
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2015-11-29 00:14:59 +00:00
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#define AUDIO_BASE 0x4000
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/*
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base clock cpu clock/32 ?
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2015-11-29 19:04:10 +00:00
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0/1: 1. channel(right): 12 bit frequency: right frequency 0 nothing, 1 high;
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3 23khz; 4 17,3; 10 6,9; 15 4.6; $60 720hz; $eff 18,0; $fff 16,9 hz)
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2015-11-29 00:14:59 +00:00
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(delay clock/32)
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2/3: 2. channel(left): 12 bit frequency
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4/5: 3. channel(both): 12 bit frequency
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6: 0..5 noise frequency 0 fast 1f slow (about 500us) 15.6ns--> clock/32 counts
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7 control (hinibble right)
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bit 0: right channel high (full cycle, else square pulse/tone)
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bit 1: left channel high
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bit 2: both channel high
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bit 3: set right tone (else noise)
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bit 4: set left channel normal
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bit 5: set both normal
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bits 30: 11 high, 10 square, 01 noise, 00 noise only when square high
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noise means switches channel to ad converter based noise algorithmen
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(white noise shift register 17bit wide, repeats after about 130000 cycles)
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probably out=!bit16, bit0=bit16 xor bit13; runs through, so start value anything than 0
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8: 1st volume: 0..3 square volume; bit 4 envelope (higher priority)
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9: 2nd volume
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10: 3rd volume
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11/12: envelope delay time 0 fast, 0xffff slow/nearly no effect (2 22us, 4 56us)
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frequency $800, envelope $10 2 times in pulse high time (4*16*16)
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13: envelope control
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0-3 one time falling
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4-7 one time rising
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8 falling
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9 one time falling
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a starts with down falling, rising; same falling time, but double/longer cycle
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b one time falling, on
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c rising
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d one time rising, on
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e rising, falling (double cycle before restart)
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f one time rising
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bit 0: once only
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bit 1: full tone
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bit 2: start rising (else falling)
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bit 3:
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*/
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/* LCD
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resolution 160x152 in 4 greys/greens
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2 256x256 sized bitplanes (2x 8kbyte ram)
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*/
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#define LCD_BASE 0x5000
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#define LCD_MODE 0x5001
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/*
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bit 3..0 (from zeropage 15)
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bit 0 set no normal screen display, seldom scrolling effects on screen;
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bytes written to somewhat actual display refresh position!?
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bytes read "random"
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bit 1,2,3 no effect
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bit 4 swaps plane intensity
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bit 5 ? display effect
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bit 6 on y auto increment (else auto x increment), reading
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bit 7 ? lcd flickering
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*/
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#define LCD_MODE_INC_Y 0x40
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#define LCD_XPOS 0x5002 /* smooth scrolling X */
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#define LCD_YPOS 0x5003 /* smooth scrolling Y */
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/*
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smooth scrolling until $c8 with 200 limit
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after 200 display if ((value & 0xf) < 8) display of (value & 0xf) - 8
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chaos lines from value + current line from plane 2 only then lines starting
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with zero (problematic 200 limit/overrun implementation!?)
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*/
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#define LCD_X 0x5004 /* x-addr */
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/*
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bit 5,6 no effect
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bit 7 0 1st/1 2nd bitplane
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*/
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#define LCD_XPOS_PLANE1 0x00
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#define LCD_XPOS_PLANE2 0x80
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#define LCD_Y 0x5005 /* y-addr */
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#define LCD_READ 0x5006 /* read from RAM (no auto inc?) */
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#define LCD_DATA 0x5007 /* write to RAM */
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2015-11-29 19:04:10 +00:00
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/* BIOS zeropage usage */
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/* locations 0x0a-0x0c, 0x0e-0x11 and 0xe8 are in use by the BIOS IRQ/NMI handlers */
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#define ZP_NMI_4800 0x0a /* content of I/O reg 4800 gets copied here each NMI */
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#define ZP_IRQ_COUNT 0x0b /* increments once per IRQ, used elsewhere in the
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BIOS for synchronisation purposes */
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#define ZP_IRQ_CTRL 0x0c /* if 0 then cartridge irq stubs will not get called */
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/* each of the following 4 increments by 1 per IRQ - it is _not_ a 32bit
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counter (see code at $ffa6 in BIOS)
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2015-12-01 15:38:00 +00:00
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these are not used elsewhere in the bios and can be (re)set as needed by
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2015-11-29 19:04:10 +00:00
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the user.
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*/
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#define ZP_IRQ_CNT1 0x0e
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#define ZP_IRQ_CNT2 0x0f
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#define ZP_IRQ_CNT3 0x10
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#define ZP_IRQ_CNT4 0x11
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#define ZP_NMI_FLAG 0xe8 /* set to 0xff each NMI */
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2015-11-29 00:14:59 +00:00
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/* constants for the conio implementation */
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#define COLOR_BLACK 0x03
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#define COLOR_WHITE 0x00
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2015-11-30 17:44:04 +00:00
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#define CH_HLINE 1
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#define CH_VLINE 2
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#define CH_CROSS 3
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#define CH_ULCORNER 4
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#define CH_URCORNER 5
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#define CH_LLCORNER 6
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#define CH_LRCORNER 7
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#define CH_TTEE 8
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#define CH_BTEE 9
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#define CH_RTEE 11
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#define CH_LTEE 12
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#define CH_ENTER 13
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#define CH_PI 18
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#define TV_NTSC 0
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#define TV_PAL 1
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#define TV_OTHER 2
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2015-11-29 00:14:59 +00:00
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/* No support for dynamically loadable drivers */
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#define DYN_DRV 0
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2020-08-26 13:51:20 +00:00
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#define JOY_DATA 0x4400 /* hw register to read the pad bits from */
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2017-08-19 17:11:28 +00:00
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/* Masks for joy_read */
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#define JOY_UP_MASK 0x01
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#define JOY_DOWN_MASK 0x02
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#define JOY_LEFT_MASK 0x04
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#define JOY_RIGHT_MASK 0x08
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#define JOY_BTN_1_MASK 0x10
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#define JOY_BTN_2_MASK 0x20
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#define JOY_BTN_3_MASK 0x40
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#define JOY_BTN_4_MASK 0x80
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#define JOY_BTN_A_MASK JOY_BTN_1_MASK
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#define JOY_BTN_B_MASk JOY_BTN_2_MASK
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#define JOY_START_MASK JOY_BTN_3_MASK
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#define JOY_SELECT_MASK JOY_BTN_4_MASK
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#define JOY_BTN_A(v) ((v) & JOY_BTN_A_MASK)
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#define JOY_BTN_B(v) ((v) & JOY_BTN_B_MASK)
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#define JOY_START(v) ((v) & JOY_START_MASK)
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#define JOY_SELECT(v) ((v) & JOY_SELECT_MASK)
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2017-07-22 13:49:34 +00:00
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2015-11-29 00:14:59 +00:00
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/* The addresses of the static drivers */
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extern void gamate_stdjoy_joy[]; /* Referred to by joy_static_stddrv[] */
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2017-07-17 21:15:05 +00:00
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void waitvsync (void);
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/* Wait for start of next frame */
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2015-11-14 12:15:29 +00:00
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2015-11-29 00:14:59 +00:00
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/* NOTE: all Gamate are "NTSC" */
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2015-11-30 17:44:04 +00:00
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#define get_tv() TV_NTSC
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2015-11-29 00:14:59 +00:00
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/* Return the video mode the machine is using. */
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2015-11-14 12:15:29 +00:00
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/* End of gamate.h */
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#endif
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