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Changes in INSTALL routine from emd/c128-vdc.s.
tmp1 was used at two places resulting in the bug that VDC_CSET was set to garbage on 16k VDC. pagecount and curpage were not reset on INSTALL resulting in non-reentrant code on static linkage of emd driver.
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@ -52,13 +52,11 @@ VDC_DATA = 31
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; ------------------------------------------------------------------------
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; Data.
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.data
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pagecount: .word 64 ; $0000-$3fff as 16k default
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curpage: .word $ffff ; currently mapped-in page (invalid)
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.bss
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pagecount: .res 1 ; $0000-$3fff as 16k default
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curpage: .res 2 ; currently mapped-in page (invalid)
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vdc_cset_save: .res 1
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window: .res 256 ; memory window
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.code
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@ -71,11 +69,15 @@ window: .res 256 ; memory window
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;
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INSTALL:
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; reset mapped-in page to invalid
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lda #$ff
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sta curpage
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sta curpage+1
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; do test for VDC presence here???
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ldx #VDC_CSET ; determine size of RAM...
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jsr vdcgetreg
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sta tmp1
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sta vdc_cset_save
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ora #%00010000
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jsr vdcputreg ; turn on 64k
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@ -94,35 +96,39 @@ INSTALL:
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lda tmp2
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jsr vdcputbyte ; restore original value of test byte
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ldx #0 ; prepare x with hi of default pagecount
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lda ptr1 ; do bytes match?
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cmp ptr1+1
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bne @have64k
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lda ptr2
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cmp ptr2+1
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bne @have64k
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ldx #VDC_CSET
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lda tmp1
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jsr vdcputreg ; restore 16/64k flag
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jmp @endok ; and leave default values for 16k
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@have64k:
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lda #<256
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ldx #>256
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lda #64 ; assumes x = 0, here -> p.c = 64
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bne @setpagecnt
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@have64k:
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txa ; assumes x = 0, here
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inx ; so that a/x becomes 0/1 -> p.c. = 256
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@setpagecnt:
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sta pagecount
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stx pagecount+1
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@endok:
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ldx #VDC_CSET ; restore 16/64k flag
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lda vdc_cset_save
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jsr vdcputreg
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lda #<EM_ERR_OK
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ldx #>EM_ERR_OK
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rts
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test64k:
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sta tmp1
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sta tmp3
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sty ptr3
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lda #0
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sta ptr3+1
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jsr settestadr1
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lda tmp1
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lda tmp3
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jsr vdcputbyte ; write $55
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jsr settestadr1
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jsr vdcgetbyte ; read here
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@ -199,6 +205,8 @@ transferin:
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lda VDC_DATA_REG ; get 2 bytes at a time to speed-up
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sta (ptr2),y ; (in fact up to 8 bytes could be fetched with special VDC config)
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iny
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@L1: bit VDC_ADDR_REG ; XXX: Test waiting for register 31
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bpl @L1
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lda VDC_DATA_REG
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sta (ptr2),y
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iny
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@ -334,6 +342,8 @@ vdcsetsrcaddr:
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dex
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tya
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stx VDC_ADDR_REG
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@L1: bit VDC_ADDR_REG ; XXX: Test waiting for register 18
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bpl @L1
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sta VDC_DATA_REG
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rts
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