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@ -37,8 +37,6 @@
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BBRx, BBSx, RMBx, SMBx, WAI, and STP are unsupported
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* BCD flag handling equals 6502 (unchecked if bug is simulated or wrong for
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6502)
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* one cycle win for fetch-modify-write instructions ignored
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(e.g., ROL abs,x takes only 6 cycles if no page break occurs)
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*/
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#include "memory.h"
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@ -629,6 +627,8 @@ static void OPC_6502_1E (void)
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unsigned Val;
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Cycles = 7;
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Addr = MemReadWord (Regs.PC+1) + Regs.XR;
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if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
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--Cycles;
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Val = MemReadByte (Addr) << 1;
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MemWriteByte (Addr, (unsigned char) Val);
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TEST_ZF (Val & 0xFF);
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@ -898,6 +898,8 @@ static void OPC_6502_3E (void)
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unsigned Val;
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Cycles = 7;
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Addr = MemReadWord (Regs.PC+1) + Regs.XR;
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if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
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--Cycles;
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Val = MemReadByte (Addr);
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ROL (Val);
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MemWriteByte (Addr, Val);
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@ -1132,6 +1134,8 @@ static void OPC_6502_5E (void)
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unsigned char Val;
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Cycles = 7;
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Addr = MemReadWord (Regs.PC+1) + Regs.XR;
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if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
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--Cycles;
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Val = MemReadByte (Addr);
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SET_CF (Val & 0x01);
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Val >>= 1;
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@ -1462,6 +1466,8 @@ static void OPC_6502_7E (void)
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unsigned Val;
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Cycles = 7;
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Addr = MemReadWord (Regs.PC+1) + Regs.XR;
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if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
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--Cycles;
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Val = MemReadByte (Addr);
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ROR (Val);
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MemWriteByte (Addr, Val);
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@ -2341,6 +2347,8 @@ static void OPC_6502_DE (void)
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unsigned char Val;
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Cycles = 7;
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Addr = MemReadWord (Regs.PC+1) + Regs.XR;
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if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
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--Cycles;
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Val = MemReadByte (Addr) - 1;
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MemWriteByte (Addr, Val);
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TEST_ZF (Val);
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@ -2648,6 +2656,8 @@ static void OPC_6502_FE (void)
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unsigned char Val;
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Cycles = 7;
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Addr = MemReadWord (Regs.PC+1) + Regs.XR;
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if (CPU != CPU_6502 && !PAGE_CROSS (Addr, Regs.XR))
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--Cycles;
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Val = MemReadByte (Addr) + 1;
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MemWriteByte (Addr, Val);
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TEST_ZF (Val);
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