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added compiler/assembler target, lib compiles

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This commit is contained in:
mrdudz 2014-11-29 15:35:20 +01:00
parent 86e6abfcd9
commit 4275b82117
12 changed files with 60 additions and 341 deletions
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0
libsrc/pce/pcengine.x → cfg/pce.cfg
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2
libsrc/Makefile
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@ -24,7 +24,7 @@ TARGETS = apple2 \
$(GEOS) \
lynx \
nes \
pcengine \
pce \
sim6502 \
sim65c02 \
supervision

2
libsrc/joystick/joy-kernel.s
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@ -109,7 +109,7 @@ inv_drv:
copy: lda (ptr1),y
iny
set: sta joy_vectors,x
sta joy_vectors,x
inx
rts

67
libsrc/pce/_heap.s
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@ -1,67 +0,0 @@
;
; Ullrich von Bassewitz, 03.06.1998
;
; Heap variables and initialization.
;
; FIXME: there should be a way to configure heap from linkerscript!
.constructor initheap, 24
.import __RAM_START__, __RAM_SIZE__, __STACKSIZE__ ; Linker generated
.import __BSS_SIZE__
.importzp sp
.data
;; old - remove
.export __horg, __hptr, __hend, __hfirst, __hlast
__horg:
.word __RAM_START__+__BSS_SIZE__+__DATA_SIZE__ ; Linker calculates this symbol
__hptr:
.word __RAM_START__+__BSS_SIZE__+__DATA_SIZE__ ; Dito
__hend:
.word __RAM_START__+__RAM_SIZE__
__hfirst:
.word 0
__hlast:
.word 0
.export __heaporg
.export __heapptr
.export __heapend
.export __heapfirst
.export __heaplast
__heaporg:
.word __RAM_START__+__BSS_SIZE__+__DATA_SIZE__ ; Linker calculates this symbol
__heapptr:
.word __RAM_START__+__BSS_SIZE__+__DATA_SIZE__ ; Linker calculates this symbol
__heapend:
.word __RAM_START__+__RAM_SIZE__
__heapfirst:
.word 0
__heaplast:
.word 0
; Initialization. Will be called from startup!
.code
initheap:
;sec
;lda sp
; lda #<(__STACKSIZE__)
; lda #<(__RAM_START__+__RAM_SIZE__)
lda #<(__RAM_START__+__BSS_SIZE__+__DATA_SIZE__)
sta __heapend
sta __hend ; old
; lda sp+1
; lda #>(__STACKSIZE__)
; lda #>(__RAM_START__+__RAM_SIZE__)
lda #>(__RAM_START__+__BSS_SIZE__+__DATA_SIZE__)
sta __heapend+1
sta __hend+1 ; old
rts

36
libsrc/pce/clrscr.s
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@ -1,27 +1,25 @@
.include "pcengine.inc"
.include "pcengine.inc"
.export _clrscr
.export _clrscr
_clrscr:
st0 #VDC_MAWR
st1 #<$0000
st2 #>$0000
st0 #VDC_MAWR
st1 #<$0000
st2 #>$0000
st0 #VDC_VWR
ldy #$40
rowloop: ldx #$80
colloop:
lda #' '
staio VDC_DATA_LO
lda #$02
staio VDC_DATA_HI
st0 #VDC_VWR
ldy #$40
rowloop: ldx #$80
colloop: lda #' '
staio VDC_DATA_LO
lda #$02
staio VDC_DATA_HI
dex
bne colloop
dey
bne rowloop
dex
bne colloop
dey
bne rowloop
rts
rts

24
libsrc/pce/conio.s
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@ -69,27 +69,27 @@ _conio_init:
;
;----------------------------------------------------------------------------
.importzp ptr1
.importzp ptr1
conio_init:
; Load font
st0 #VDC_MAWR
st0 #VDC_MAWR
st1 #<$2000
st2 #>$2000
; ptr to font data
lda #<font
sta ptr1
lda #>font
sta ptr1+1
lda #<font
sta ptr1
lda #>font
sta ptr1+1
st0 #VDC_VWR ; VWR
ldy #$80 ; 128 chars
charloop: ldx #$08 ; 8 bytes/char
lineloop:
;;lda [$00] ; read font byte
ldaind ptr1
lda (ptr1)
staio VDC_DATA_LO ; bitplane 0
stzio VDC_DATA_HI ; bitplane 1
@ -110,13 +110,13 @@ conio_init:
dey
bne charloop ; next character
ldx #0
stx BGCOLOR
inx
stx CHARCOLOR
ldx #0
stx BGCOLOR
inx
stx CHARCOLOR
rts
.rodata
.rodata
font: .include "vga.inc"

238
libsrc/pce/huc6280.inc
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@ -1,238 +0,0 @@
;
; HuC6280 additional opcodes (use with --cpu 65C02)
;
; WARNING: THIS IS __NOT__ COMPLETE !!!
;
;; lda abs
.macro ldaio arg1
.byte $ad
.word arg1
.endmacro
;; sta abs
.macro staio arg1
.byte $8d
.word arg1
.endmacro
.macro stzio arg1
.byte $9c
.word arg1
.endmacro
.macro cla
.byte $62
.endmacro
.macro clx
.byte $82
.endmacro
;; lda (zp)
.macro ldaind arg1
.byte $b2
.byte arg1
.endmacro
.macro cly
.byte $c2
.endmacro
.macro st0 arg1
.if (.match (.left (1, arg1), #))
; called with immidiate operand
.byte $03
.byte (.right (.tcount (arg1)-1, arg1))
.else
.error "illegal address mode"
.endif
.endmacro
.macro st1 arg1
.if (.match (.left (1, arg1), #))
; called with immidiate operand
.byte $13
.byte (.right (.tcount (arg1)-1, arg1))
.else
.error "illegal address mode"
.endif
.endmacro
.macro st2 arg1
.if (.match (.left (1, arg1), #))
; called with immidiate operand
.byte $23
.byte (.right (.tcount (arg1)-1, arg1))
.else
.error "illegal address mode"
.endif
.endmacro
; tam #$xx
.macro tam arg1
.if (.match (.left (1, arg1), #))
; called with immidiate operand
.byte $53
.byte 1<<(.right (.tcount (arg1)-1, arg1))
.else
.error "illegal address mode"
.endif
.endmacro
; tii x,y,z
.macro tii arg1,arg2,arg3
.byte $73
.word arg1,arg2,arg3
.endmacro
.macro csh
.byte $d4
.endmacro
.macro set
.byte $f4
.endmacro
.macro _rmb0 arg1
.byte $07
.byte arg1
.endmacro
.macro _rmb1 arg1
.byte $17
.byte arg1
.endmacro
.macro _rmb2 arg1
.byte $27
.byte arg1
.endmacro
.macro _rmb3 arg1
.byte $37
.byte arg1
.endmacro
.macro _rmb4 arg1
.byte $47
.byte arg1
.endmacro
.macro _rmb5 arg1
.byte $57
.byte arg1
.endmacro
.macro _rmb6 arg1
.byte $67
.byte arg1
.endmacro
.macro _rmb7 arg1
.byte $77
.byte arg1
.endmacro
.macro _smb0 arg1
.byte $87
.byte arg1
.endmacro
.macro _smb1 arg1
.byte $97
.byte arg1
.endmacro
.macro _smb2 arg1
.byte $a7
.byte arg1
.endmacro
.macro _smb3 arg1
.byte $b7
.byte arg1
.endmacro
.macro _smb4 arg1
.byte $c7
.byte arg1
.endmacro
.macro _smb5 arg1
.byte $d7
.byte arg1
.endmacro
.macro _smb6 arg1
.byte $e7
.byte arg1
.endmacro
.macro _smb7 arg1
.byte $f7
.byte arg1
.endmacro
.macro _bbr0 arg1,arg2
.byte $0f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs0 arg1,arg2
.byte $8f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbr1 arg1,arg2
.byte $1f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs1 arg1,arg2
.byte $9f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbr2 arg1,arg2
.byte $2f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs2 arg1,arg2
.byte $af ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbr3 arg1,arg2
.byte $3f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs3 arg1,arg2
.byte $bf ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbr4 arg1,arg2
.byte $4f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs4 arg1,arg2
.byte $cf ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbr5 arg1,arg2
.byte $5f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs5 arg1,arg2
.byte $df ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbr6 arg1,arg2
.byte $6f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs6 arg1,arg2
.byte $ef ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbr7 arg1,arg2
.byte $7f ;;,arg1
.byte arg1
.byte <((arg2)-(*+1))
.endmacro
.macro _bbs7 arg1,arg2
.byte $ff
.byte arg1
.byte <((arg2)-(*+1))
.endmacro

21
libsrc/pce/pcengine.inc
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@ -1,6 +1,4 @@
.include "huc6280.inc"
; Write VDC register
.macro VREG arg1,arg2
st0 #arg1
@ -72,4 +70,21 @@ IRQ_MASK = $1402
IRQ_STATUS = $1403
CDR_MEM_DISABLE = $1803
CDR_MEM_ENABLE = $1807
CDR_MEM_ENABLE = $1807
;; lda abs
.macro ldaio arg1
.byte $ad
.word arg1
.endmacro
;; sta abs
.macro staio arg1
.byte $8d
.word arg1
.endmacro
;; stz abs
.macro stzio arg1
.byte $9c
.word arg1
.endmacro

4
src/ca65/main.c
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@ -303,6 +303,10 @@ static void SetSys (const char* Sys)
NewSymbol ("__SIM65C02__", 1);
break;
case TGT_PCENGINE:
NewSymbol ("__PCE__", 1);
break;
default:
AbEnd ("Invalid target name: `%s'", Sys);

4
src/cc65/main.c
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@ -258,6 +258,10 @@ static void SetSys (const char* Sys)
DefineNumericMacro ("__SIM65C02__", 1);
break;
case TGT_PCENGINE:
DefineNumericMacro ("__PCE__", 1);
break;
default:
AbEnd ("Unknown target system type %d", Target);
}

2
src/common/target.c
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@ -142,6 +142,7 @@ static const TargetEntry TargetMap[] = {
{ "module", TGT_MODULE },
{ "nes", TGT_NES },
{ "none", TGT_NONE },
{ "pce", TGT_PCENGINE },
{ "pet", TGT_PET },
{ "plus4", TGT_PLUS4 },
{ "sim6502", TGT_SIM6502 },
@ -180,6 +181,7 @@ static const TargetProperties PropertyTable[TGT_COUNT] = {
{ "lynx", CPU_65C02, BINFMT_BINARY, CTNone },
{ "sim6502", CPU_6502, BINFMT_BINARY, CTNone },
{ "sim65c02", CPU_65C02, BINFMT_BINARY, CTNone },
{ "pce", CPU_HUC6280, BINFMT_BINARY, CTNone },
};
/* Target system */

1
src/common/target.h
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@ -77,6 +77,7 @@ typedef enum {
TGT_LYNX,
TGT_SIM6502,
TGT_SIM65C02,
TGT_PCENGINE,
TGT_COUNT /* Number of target systems */
} target_t;