6502/cc65
1
0
Fork 0
mirror of https://github.com/cc65/cc65.git synced 2024-12-23 19:29:37 +00:00
Code Issues Projects Releases Wiki Activity

Make PIA upper case for orthogonality.

Browse Source 
git-svn-id: svn://svn.cc65.org/cc65/trunk@4586 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
uz 2010-02-12 11:07:07 +00:00
parent 6a712d8b9e
commit 49f6f3972b
1 changed files with 17 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
libsrc/c64/c64-c256k.s
View File

@ -39,7 +39,7 @@
BASE = $4000
PAGES = 3 * 256
TARGETLOC = $200 ; Target location for copy/check code
pia = $DFC0
PIA = $DFC0
; ------------------------------------------------------------------------
; Data.
@ -52,13 +52,13 @@ pia = $DFC0
template:
.org ::TARGETLOC ; Assemble for target location
entry:
stx pia
stx PIA
stashop = $91 ; 'sta' opcode
operation := * ; Location and opcode is patched at runtime
address := *+1
lda ($00),y
ldx #$dc
stx pia
stx PIA
rts
.reloc
.endproc
@ -71,7 +71,7 @@ entry:
ldy #$00 ; Assume hardware not present
lda #$fc
sta pia
sta PIA
lda $01
tax
and #$f8
@ -87,7 +87,7 @@ entry:
iny
done: stx $01
ldx #$dc
stx pia
stx PIA
rts
.reloc
.endproc
@ -115,36 +115,36 @@ backup: .res .max (.sizeof (copy), .sizeof (check))
;
INSTALL:
lda pia+1 ; Select Peripheral Registers
lda PIA+1 ; Select Peripheral Registers
ora #4
sta pia+1
sta PIA+1
tax
lda pia+3
lda PIA+3
ora #4
sta pia+3
sta PIA+3
tay
lda #$DC ; Set the default memory bank data
sta pia
sta PIA
lda #$FE
sta pia+2
sta PIA+2
txa ; Select Data Direction Registers
and #$FB
sta pia+1
sta PIA+1
tya
and #$FB
sta pia+3
sta PIA+3
lda #$FF ; Set the ports to output
sta pia
sta pia+2
sta PIA
sta PIA+2
txa
and #$C7
ora #$30 ; Set CA1 and
sta pia+1 ; select Peripheral Registers
sty pia+3
sta PIA+1 ; select Peripheral Registers
sty PIA+3
jsr backup_and_setup_check_routine
jsr check::entry