6502/cc65
1
0
Fork 0
mirror of https://github.com/cc65/cc65.git synced 2024-12-24 11:31:31 +00:00
Code Issues Projects Releases Wiki Activity

Fixed several dangling pointer bugs in 65C0 2optimizations

Browse Source 
git-svn-id: svn://svn.cc65.org/cc65/trunk@587 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
cuz 2000-12-24 14:37:18 +00:00
parent 45de0a49ec
commit 51e5a7cf84
1 changed files with 42 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
src/cc65/optimize.c
View File

@ -3589,15 +3589,15 @@ static void OptBitOps (void)
/* Search for /* Search for
* *
* lda xxx * lda xxx
* and #$yy ; adc/eor/ora * and #$yy ; adc/eor/ora
* sta xxx * sta xxx
* *
* and replace it by * and replace it by
* *
* lda #$yy * lda #$yy
* and xxx * and xxx
* sta xxx * sta xxx
* *
* While this saves nothing here, it transforms the code to contain an * While this saves nothing here, it transforms the code to contain an
* explicit register load that may be removed by the basic block * explicit register load that may be removed by the basic block
@ -3613,70 +3613,68 @@ static void OptBitOps (void)
if (LineMatch (L2[0], "\tand\t#$")) { if (LineMatch (L2[0], "\tand\t#$")) {
unsigned Val = GetHexNum (L2[0]->Line+7); unsigned Val = GetHexNum (L2[0]->Line+7);
if (Val == 0x00) { if (Val == 0x00) {
/* AND with 0x00, remove the mem access */ /* AND with 0x00, remove the mem access */
FreeLine (L); FreeLine (L);
FreeLine (L2[1]); FreeLine (L2[1]);
/* Replace the AND by a load */ /* Replace the AND by a load */
L = ReplaceLine (L2[0], "\tlda\t#$%02X", Val); L = ReplaceLine (L2[0], "\tlda\t#$%02X", Val);
} else if (Val == 0xFF) { } else if (Val == 0xFF) {
/* AND with 0xFF, just load the value from memory */ /* AND with 0xFF, just load the value from memory */
FreeLines (L2[0], L2[1]); FreeLines (L2[0], L2[1]);
} else if (CPU == CPU_65C02 && } else if (CPU == CPU_65C02 &&
!IsXAddrMode (L) && !IsXAddrMode (L) &&
!IsYAddrMode (L) && !IsYAddrMode (L) &&
!RegAUsed (L2[1])) { !RegAUsed (L2[1])) {
/* Replace by trb */ /* Replace by trb */
ReplaceLine (L, "\tlda\t#$%02X", (~Val) & 0xFF); ReplaceLine (L, "\tlda\t#$%02X", (~Val) & 0xFF);
ReplaceLine (L2[0], "\ttrb\t%s", L2[1]->Line+5); L = ReplaceLine (L2[0], "\ttrb\t%s", L2[1]->Line+5);
FreeLine (L2[1]); FreeLine (L2[1]);
L = L2[0];
} else { } else {
/* Just reorder */ /* Just reorder */
L = ReplaceLine (L, "\tlda\t#$%02X", Val); ReplaceLine (L, "\tlda\t#$%02X", Val);
ReplaceLine (L2[0], "\tand\t%s", L2[1]->Line+5); ReplaceLine (L2[0], "\tand\t%s", L2[1]->Line+5);
L = L2[1]; L = L2[1];
} }
} else if (LineMatch (L2[0], "\tora\t#$")) { } else if (LineMatch (L2[0], "\tora\t#$")) {
unsigned Val = GetHexNum (L2[0]->Line+7); unsigned Val = GetHexNum (L2[0]->Line+7);
if (Val == 0x00) { if (Val == 0x00) {
/* ORA with 0x00, just load the value from memory */ /* ORA with 0x00, just load the value from memory */
FreeLines (L2[0], L2[1]); FreeLines (L2[0], L2[1]);
} else if (Val == 0xFF) { } else if (Val == 0xFF) {
/* ORA with 0xFF, replace by a store of $FF */ /* ORA with 0xFF, replace by a store of $FF */
FreeLine (L); FreeLine (L);
ReplaceLine (L2[0], "\tlda\t#$FF"); L = ReplaceLine (L2[0], "\tlda\t#$FF");
} else if (CPU == CPU_65C02 && } else if (CPU == CPU_65C02 &&
!IsXAddrMode (L) && !IsXAddrMode (L) &&
!IsYAddrMode (L) && !IsYAddrMode (L) &&
!RegAUsed (L2[1])) { !RegAUsed (L2[1])) {
/* Replace by trb */ /* Replace by trb */
ReplaceLine (L, "\tlda\t#$%02X", Val); ReplaceLine (L, "\tlda\t#$%02X", Val);
ReplaceLine (L2[0], "\ttsb\t%s", L2[1]->Line+5); L = ReplaceLine (L2[0], "\ttsb\t%s", L2[1]->Line+5);
FreeLine (L2[1]); FreeLine (L2[1]);
L = L2[0];
} else { } else {
/* Just reorder */ /* Just reorder */
L = ReplaceLine (L, "\tlda\t#$%02X", Val); ReplaceLine (L, "\tlda\t#$%02X", Val);
ReplaceLine (L2[0], "\tora\t%s", L2[1]->Line+5); ReplaceLine (L2[0], "\tora\t%s", L2[1]->Line+5);
L = L2[1]; L = L2[1];