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https://github.com/cc65/cc65.git
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Check also sreg in OptSize1. Added information about shortcut functions for
longs that clear the high word of the right operand on entry. git-svn-id: svn://svn.cc65.org/cc65/trunk@4024 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
uz
parent
b1f772e9be
commit
582506b7fc
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@ -164,6 +164,7 @@ static const FuncInfo FuncInfoTable[] = {
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{ "mulax9", REG_AX, REG_AX | REG_PTR1 },
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{ "negax", REG_AX, REG_AX },
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{ "push0", REG_NONE, REG_AXY },
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{ "push0ax", REG_AX, REG_Y | REG_SREG },
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{ "push1", REG_NONE, REG_AXY },
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{ "push2", REG_NONE, REG_AXY },
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{ "push3", REG_NONE, REG_AXY },
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@ -210,6 +211,7 @@ static const FuncInfo FuncInfoTable[] = {
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{ "steaxysp", REG_EAXY, REG_Y },
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{ "subeq0sp", REG_AX, REG_AXY },
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{ "subeqysp", REG_AXY, REG_AXY },
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{ "tosadd0ax", REG_AX, REG_EAXY | REG_TMP1 },
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{ "tosadda0", REG_A, REG_AXY },
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{ "tosaddax", REG_AX, REG_AXY },
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{ "tosaddeax", REG_EAX, REG_EAXY | REG_TMP1 },
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@ -219,9 +221,10 @@ static const FuncInfo FuncInfoTable[] = {
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{ "tosasleax", REG_EAX, REG_EAXY | REG_TMP1 },
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{ "tosasrax", REG_AX, REG_AXY | REG_TMP1 },
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{ "tosasreax", REG_EAX, REG_EAXY | REG_TMP1 },
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{ "tosdiv0ax", REG_AX, REG_ALL },
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{ "tosdiva0", REG_AY, REG_ALL },
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{ "tosdivax", REG_AXY, REG_ALL },
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{ "tosdiveax", REG_EAXY, REG_ALL },
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{ "tosdiveax", REG_EAX, REG_ALL },
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{ "toseq00", REG_NONE, REG_AXY | REG_SREG },
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{ "toseqa0", REG_A, REG_AXY | REG_SREG },
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{ "toseqax", REG_AX, REG_AXY | REG_SREG },
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@ -245,6 +248,9 @@ static const FuncInfo FuncInfoTable[] = {
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{ "toslta0", REG_A, REG_AXY | REG_SREG },
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{ "tosltax", REG_AX, REG_AXY | REG_SREG },
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{ "toslteax", REG_EAX, REG_AXY | REG_PTR1 },
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{ "tosmod0ax", REG_AX, REG_ALL },
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{ "tosmodeax", REG_EAX, REG_ALL },
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{ "tosmul0ax", REG_AX, REG_ALL },
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{ "tosmula0", REG_AX, REG_ALL },
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{ "tosmulax", REG_AX, REG_ALL },
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{ "tosmuleax", REG_EAX, REG_ALL },
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@ -258,9 +264,11 @@ static const FuncInfo FuncInfoTable[] = {
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{ "tosshleax", REG_A, REG_EAXY | REG_TMP1 },
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{ "tosshrax", REG_A, REG_AXY | REG_TMP1 },
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{ "tosshreax", REG_A, REG_EAXY | REG_TMP1 },
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{ "tossub0ax", REG_AX, REG_EAXY },
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{ "tossuba0", REG_A, REG_AXY },
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{ "tossubax", REG_AX, REG_AXY },
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{ "tossubeax", REG_EAX, REG_EAXY },
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{ "tosudiv0ax", REG_AX, REG_ALL & ~REG_SAVE },
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{ "tosudiva0", REG_A, REG_EAXY | REG_PTR1 }, /* also ptr4 */
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{ "tosudivax", REG_AX, REG_EAXY | REG_PTR1 }, /* also ptr4 */
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{ "tosudiveax", REG_EAX, REG_ALL & ~REG_SAVE },
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@ -280,9 +288,11 @@ static const FuncInfo FuncInfoTable[] = {
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{ "tosulta0", REG_A, REG_AXY | REG_SREG },
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{ "tosultax", REG_AX, REG_AXY | REG_SREG },
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{ "tosulteax", REG_EAX, REG_AXY | REG_PTR1 },
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{ "tosumod0ax", REG_AX, REG_ALL & ~REG_SAVE },
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{ "tosumoda0", REG_A, REG_EAXY | REG_PTR1 }, /* also ptr4 */
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{ "tosumodax", REG_AX, REG_EAXY | REG_PTR1 }, /* also ptr4 */
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{ "tosumodeax", REG_EAX, REG_ALL & ~REG_SAVE },
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{ "tosumul0ax", REG_AX, REG_ALL },
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{ "tosumula0", REG_AX, REG_ALL },
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{ "tosumulax", REG_AX, REG_ALL },
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{ "tosumuleax", REG_EAX, REG_ALL },
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@ -1554,6 +1554,7 @@ static unsigned RunOptGroup6 (CodeSeg* S)
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* may have opened new oportunities.
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*/
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Changes += RunOptFunc (S, &DOptUnusedLoads, 1);
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Changes += RunOptFunc (S, &DOptUnusedStores, 1);
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Changes += RunOptFunc (S, &DOptJumpTarget1, 5);
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Changes += RunOptFunc (S, &DOptStore5, 1);
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}
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@ -898,7 +898,9 @@ unsigned OptUnusedStores (CodeSeg* S)
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/* Remember, we had changes */
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++Changes;
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/* Continue with next insn */
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continue;
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}
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}
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@ -59,7 +59,7 @@
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typedef struct CallDesc CallDesc;
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struct CallDesc {
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const char* LongFunc; /* Long function name */
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short A, X, Y; /* Register contents */
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RegContents Regs; /* Register contents */
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unsigned Flags; /* Flags from above */
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const char* ShortFunc; /* Short function name */
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};
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@ -68,85 +68,655 @@ struct CallDesc {
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* name, entries are sorted best match first, so when searching linear for
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* a match, the first one can be used because it is also the best one (or
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* at least none of the following ones are better).
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* Note^2: Ptr1 and Tmp1 aren't evaluated, because runtime routines don't
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* expect parameters here.
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*/
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static const CallDesc CallTable [] = {
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/* Name A register X register Y register flags replacement */
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{ "addeqysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, F_NONE, "addeq0sp" },
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{ "laddeqysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, F_NONE, "laddeq0sp" },
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{ "ldaxidx", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, F_NONE, "ldaxi" },
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{ "ldaxysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, F_NONE, "ldax0sp" },
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{ "ldeaxidx", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, F_NONE, "ldeaxi" },
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{ "ldeaxysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, F_NONE, "ldeax0sp" },
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{ "lsubeqysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, F_NONE, "lsubeq0sp" },
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{ "pusha", 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, F_SLOWER, "pushc0" },
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{ "pusha", 1, UNKNOWN_REGVAL, UNKNOWN_REGVAL, F_SLOWER, "pushc1" },
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{ "pusha", 2, UNKNOWN_REGVAL, UNKNOWN_REGVAL, F_SLOWER, "pushc2" },
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{ "pushax", 0, 0, UNKNOWN_REGVAL, F_NONE, "push0" },
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{ "pushax", 1, 0, UNKNOWN_REGVAL, F_SLOWER, "push1" },
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{ "pushax", 2, 0, UNKNOWN_REGVAL, F_SLOWER, "push2" },
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{ "pushax", 3, 0, UNKNOWN_REGVAL, F_SLOWER, "push3" },
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{ "pushax", 4, 0, UNKNOWN_REGVAL, F_SLOWER, "push4" },
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{ "pushax", 5, 0, UNKNOWN_REGVAL, F_SLOWER, "push5" },
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{ "pushax", 6, 0, UNKNOWN_REGVAL, F_SLOWER, "push6" },
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{ "pushax", 7, 0, UNKNOWN_REGVAL, F_SLOWER, "push7" },
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{ "pushax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "pusha0" },
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{ "pushax", UNKNOWN_REGVAL, 0xFF, UNKNOWN_REGVAL, F_SLOWER, "pushaFF" },
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{ "pushaysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, F_NONE, "pusha0sp" },
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{ "pushwidx", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, F_NONE, "pushw" },
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{ "pushwysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, F_NONE, "pushw0sp" },
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{ "staxysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, F_NONE, "stax0sp" },
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{ "steaxysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, F_NONE, "steax0sp" },
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{ "subeqysp", UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, F_NONE, "subeq0sp" },
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{ "tosaddax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosadda0" },
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{ "tosandax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosanda0" },
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{ "tosdivax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosdiva0" },
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{ "toseqax", 0, 0, UNKNOWN_REGVAL, F_NONE, "toseq00" },
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{ "toseqax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "toseqa0" },
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{ "tosgeax", 0, 0, UNKNOWN_REGVAL, F_NONE, "tosge00" },
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{ "tosgeax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosgea0" },
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{ "tosgtax", 0, 0, UNKNOWN_REGVAL, F_NONE, "tosgt00" },
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{ "tosgtax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosgta0" },
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{ "tosicmp", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosicmp0" },
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{ "tosleax", 0, 0, UNKNOWN_REGVAL, F_NONE, "tosle00" },
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{ "tosleax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "toslea0" },
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{ "tosltax", 0, 0, UNKNOWN_REGVAL, F_NONE, "toslt00" },
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{ "tosltax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "toslta0" },
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{ "tosmodax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosmoda0" },
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{ "tosmulax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosmula0" },
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{ "tosneax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosnea0" },
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{ "tosorax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosora0" },
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{ "tosrsubax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosrsuba0" },
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{ "tossubax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tossuba0" },
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{ "tosudivax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosudiva0" },
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{ "tosugeax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosugea0" },
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{ "tosugtax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosugta0" },
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{ "tosuleax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosulea0" },
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{ "tosultax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosulta0" },
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{ "tosumodax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosumoda0" },
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{ "tosumulax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosumula0" },
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{ "tosxorax", UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, F_NONE, "tosxora0" },
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{
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"addeqysp",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"addeq0sp"
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},{
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"laddeqysp",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"laddeq0sp"
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},{
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"ldaxidx",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"ldaxi"
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},{
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"ldaxysp",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"ldax0sp"
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},{
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"ldeaxidx",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"ldeaxi"
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},{
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"ldeaxysp",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"ldeax0sp"
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},{
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"lsubeqysp",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"lsubeq0sp"
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},{
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"pusha",
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{
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/* A X Y SRegLo */
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0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"pushc0"
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},{
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"pusha",
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{
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/* A X Y SRegLo */
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1, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"pushc1"
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},{
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"pusha",
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{
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/* A X Y SRegLo */
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2, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"pushc2"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"push0"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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1, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"push1"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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2, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"push2"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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3, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"push3"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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4, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"push4"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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5, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"push5"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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6, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"push6"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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7, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_SLOWER,
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"push7"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
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UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
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/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
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UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
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},
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F_NONE,
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"pusha0"
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},{
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"pushax",
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{
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/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0xFF, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_SLOWER,
|
||||
"pushaFF"
|
||||
},{
|
||||
"pushaysp",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"pusha0sp"
|
||||
},{
|
||||
"pusheax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"push0ax"
|
||||
},{
|
||||
"pushwidx",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, 1, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"pushw"
|
||||
},{
|
||||
"pushwysp",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, 3, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"pushw0sp"
|
||||
},{
|
||||
"staxysp",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"stax0sp"
|
||||
},{
|
||||
"steaxysp",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"steax0sp"
|
||||
},{
|
||||
"subeqysp",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"subeq0sp"
|
||||
},{
|
||||
"tosaddax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosadda0"
|
||||
},{
|
||||
"tosaddeax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosadd0ax"
|
||||
},{
|
||||
"tosandax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosanda0"
|
||||
},{
|
||||
"tosdivax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosdiva0"
|
||||
},{
|
||||
"tosdiveax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosdiv0ax"
|
||||
},{
|
||||
"toseqax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"toseq00"
|
||||
},{
|
||||
"toseqax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"toseqa0"
|
||||
},{
|
||||
"tosgeax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosge00"
|
||||
},{
|
||||
"tosgeax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosgea0"
|
||||
},{
|
||||
"tosgtax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosgt00"
|
||||
},{
|
||||
"tosgtax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosgta0"
|
||||
},{
|
||||
"tosicmp",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosicmp0"
|
||||
},{
|
||||
"tosleax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosle00"
|
||||
},{
|
||||
"tosleax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"toslea0"
|
||||
},{
|
||||
"tosltax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
0, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"toslt00"
|
||||
},{
|
||||
"tosltax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"toslta0"
|
||||
},{
|
||||
"tosmodax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosmoda0"
|
||||
},{
|
||||
"tosmodeax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosmod0ax"
|
||||
},{
|
||||
"tosmulax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosmula0"
|
||||
},{
|
||||
"tosmuleax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosmul0ax"
|
||||
},{
|
||||
"tosneax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosnea0"
|
||||
},{
|
||||
"tosorax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosora0"
|
||||
},{
|
||||
"tosrsubax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosrsuba0"
|
||||
},{
|
||||
"tossubax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tossuba0"
|
||||
},{
|
||||
"tossubeax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tossub0ax"
|
||||
},{
|
||||
"tosudivax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosudiva0"
|
||||
},{
|
||||
"tosudiveax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosudiv0ax"
|
||||
},{
|
||||
"tosugeax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosugea0"
|
||||
},{
|
||||
"tosugtax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosugta0"
|
||||
},{
|
||||
"tosuleax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosulea0"
|
||||
},{
|
||||
"tosultax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosulta0"
|
||||
},{
|
||||
"tosumodax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosumoda0"
|
||||
},{
|
||||
"tosumodeax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosumod0ax"
|
||||
},{
|
||||
"tosumulax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosumula0"
|
||||
},{
|
||||
"tosumuleax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, 0,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
0, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosumul0ax"
|
||||
},{
|
||||
"tosxorax",
|
||||
{
|
||||
/* A X Y SRegLo */
|
||||
UNKNOWN_REGVAL, 0, UNKNOWN_REGVAL, UNKNOWN_REGVAL,
|
||||
/* SRegHi Ptr1Lo Ptr1Hi Tmp1 */
|
||||
UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL, UNKNOWN_REGVAL
|
||||
},
|
||||
F_NONE,
|
||||
"tosxora0"
|
||||
},
|
||||
|
||||
#if 0
|
||||
"tosadd0ax", /* tosaddeax, sreg = 0 */
|
||||
"laddeqa", /* laddeq, sreg = 0, x = 0 */
|
||||
"laddeq1", /* laddeq, sreg = 0, x = 0, a = 1 */
|
||||
"tosand0ax", /* tosandeax, sreg = 0 */
|
||||
"tosdiv0ax", /* tosdiveax, sreg = 0 */
|
||||
"tosmod0ax", /* tosmodeax, sreg = 0 */
|
||||
"tosmul0ax", /* tosmuleax, sreg = 0 */
|
||||
"tosumul0ax", /* tosumuleax, sreg = 0 */
|
||||
"tosor0ax", /* tosoreax, sreg = 0 */
|
||||
"push0ax", /* pusheax, sreg = 0 */
|
||||
"tosrsub0ax", /* tosrsubeax, sreg = 0 */
|
||||
"tosshl0ax", /* tosshleax, sreg = 0 */
|
||||
"tosasl0ax", /* tosasleax, sreg = 0 */
|
||||
"tosshr0ax", /* tosshreax, sreg = 0 */
|
||||
"tosasr0ax", /* tosasreax, sreg = 0 */
|
||||
"tossub0ax", /* tossubeax, sreg = 0 */
|
||||
"lsubeqa", /* lsubeq, sreg = 0, x = 0 */
|
||||
"lsubeq1", /* lsubeq, sreg = 0, x = 0, a = 1 */
|
||||
"tosudiv0ax", /* tosudiveax, sreg = 0 */
|
||||
"tosumod0ax", /* tosumodeax, sreg = 0 */
|
||||
"tosxor0ax", /* tosxoreax, sreg = 0 */
|
||||
#endif
|
||||
};
|
||||
|
|
@ -196,6 +766,16 @@ static const CallDesc* FindCall (const char* Name)
|
|||
|
||||
|
||||
|
||||
static int RegMatch (short Expected, short Actual)
|
||||
/* Check for a register match. If Expected has a value, it must be identical
|
||||
* to Actual.
|
||||
*/
|
||||
{
|
||||
return RegValIsUnknown (Expected) || (Expected == Actual);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Code */
|
||||
/*****************************************************************************/
|
||||
|
|
@ -230,6 +810,9 @@ unsigned OptSize1 (CodeSeg* S)
|
|||
/* Check if it's a subroutine call */
|
||||
if (E->OPC == OP65_JSR && (D = FindCall (E->Arg)) != 0) {
|
||||
|
||||
/* Get input register info for this insn */
|
||||
const RegContents* In = &E->RI->In;
|
||||
|
||||
/* FindCall finds the first entry that matches our function name.
|
||||
* The names are listed in "best match" order, so search for the
|
||||
* first one, that fulfills our conditions.
|
||||
|
|
@ -239,10 +822,12 @@ unsigned OptSize1 (CodeSeg* S)
|
|||
/* Check the registers and allow slower code only if
|
||||
* optimizing for size.
|
||||
*/
|
||||
if ((D->A < 0 || D->A == E->RI->In.RegA) &&
|
||||
(D->X < 0 || D->X == E->RI->In.RegX) &&
|
||||
(D->Y < 0 || D->Y == E->RI->In.RegY) &&
|
||||
(OptForSize || (D->Flags & F_SLOWER) == 0)) {
|
||||
if ((OptForSize || (D->Flags & F_SLOWER) == 0) &&
|
||||
RegMatch (D->Regs.RegA, In->RegA) &&
|
||||
RegMatch (D->Regs.RegX, In->RegX) &&
|
||||
RegMatch (D->Regs.RegY, In->RegY) &&
|
||||
RegMatch (D->Regs.SRegLo, In->SRegLo) &&
|
||||
RegMatch (D->Regs.SRegHi, In->SRegHi)) {
|
||||
|
||||
/* Ok, match for all conditions */
|
||||
CodeEntry* X;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user