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Merge pull request #2414 from SvenMichaelKlose/master 

vic-asm.cfg: Fix size of MAIN to end at $1E00.
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Bob Andrews 2024-03-09 12:00:42 +01:00 committed by GitHub
parent 5c3ff714ae 1fe12f112e
commit 60c75bdb54
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GPG Key ID: B5690EEEBB952194
3 changed files with 45 additions and 1 deletions
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21
cfg/vic20-asm-32k.cfg Normal file
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@ -0,0 +1,21 @@
# Assembly program configuration for expanded VICs (>= +8K).
FEATURES {
STARTADDRESS: default = $1201;
}
SYMBOLS {
__LOADADDR__: type = import;
}
MEMORY {
ZP: file = "", start = $0002, size = $001A, define = yes;
LOADADDR: file = %O, start = %S - 2, size = $0002;
MAIN: file = %O, start = %S, size = $8000 - %S;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro;
CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw;
BSS: load = MAIN, type = bss, optional = yes, define = yes;
}

21
cfg/vic20-asm-3k.cfg Normal file
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@ -0,0 +1,21 @@
# Assembly program configuration for expanded VICs (+3K only).
FEATURES {
STARTADDRESS: default = $0401;
}
SYMBOLS {
__LOADADDR__: type = import;
}
MEMORY {
ZP: file = "", start = $0002, size = $001A, define = yes;
LOADADDR: file = %O, start = %S - 2, size = $0002;
MAIN: file = %O, start = %S, size = $1E00 - %S;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro;
CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw;
BSS: load = MAIN, type = bss, optional = yes, define = yes;
}

4
cfg/vic20-asm.cfg
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@ -1,3 +1,5 @@
# Assembly program configuration for unexpanded VICs.
FEATURES {
STARTADDRESS: default = $1001;
}
@ -7,7 +9,7 @@ SYMBOLS {
MEMORY {
ZP: file = "", start = $0002, size = $001A, define = yes;
LOADADDR: file = %O, start = %S - 2, size = $0002;
MAIN: file = %O, start = %S, size = $0DF3 - %S;
MAIN: file = %O, start = %S, size = $1E00 - %S;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes;