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Fixed and improved some pce comments.

This commit is contained in:
Greg King 2015-11-17 09:14:15 -05:00 committed by Oliver Schmidt
parent 2cc822b44e
commit 959eff34a3
15 changed files with 61 additions and 55 deletions
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13
asminc/pce.inc
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@ -13,8 +13,8 @@ CH_VLINE = 2
VDC_MAWR = 0 ; Memory Address Write Register
VDC_MARR = 1 ; Memory Address Read Register
VDC_VWR = 2 ; VRAM Write Register (write only)
VDC_VRR = 2 ; VRAM Read Register (read only)
VDC_VWR = 2 ; VRAM Write Register
VDC_VRR = 2 ; VRAM Read Register
VDC_UNK03 = 3 ; (unknown)
VDC_UNK04 = 4 ; (unknown)
VDC_CR = 5 ; Control Register
@ -35,8 +35,7 @@ VDC_SATB = 19 ; Sprite Attribute Table
; VDC port
; Note: The zero-page addressing mode is redirected to page $20.
; Therefore, absolute addressing mode must be used when writing to this port.
; We force it by using mirror locations that are outside of zero page.
; We avoid it by using mirror locations that are outside of the zero page.
VDC_CTRL := $0200
VDC_DATA_LO := $0202
@ -45,7 +44,7 @@ VDC_DATA_HI := $0203
; HuC6260 -- Video Color Encoder (VCE)
; The DAC has a palette of 512 colours.
; The bitmap of the palette data is this: 0000000gggrrrbbb.
; The bitmap of that data is 0000000gggrrrbbb (Green, Red, Blue).
; You can read and write the DAC registers.
VCE := $0400 ; base
@ -86,8 +85,8 @@ IRQ_STATUS := $1403
CDR_MEM_DISABLE := $1803
CDR_MEM_ENABLE := $1807
; Write VDC register
.macro VREG arg1,arg2
; Write to a VDC register.
.macro VREG arg1, arg2
st0 #arg1
st1 #<(arg2)
st2 #>(arg2)

4
cfg/pce.cfg
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@ -4,9 +4,9 @@ SYMBOLS {
__STACKSIZE__: type = weak, value = $0300; # 3 pages stack
}
MEMORY {
ZP: file = "", start = $0000, size = $0100, define = yes;
ZP: file = "", start = $0000, define = yes, size = $0100;
# RAM bank
MAIN: file = "", start = $2200, size = $1E00 - __STACKSIZE__, define = yes;
MAIN: file = "", start = $2200, define = yes, size = $1E00 - __STACKSIZE__;
# ROM banks, before swapping, and after mapping
ROM: file = %O, start = $10000 - __CARTSIZE__, size = __CARTSIZE__, fill = yes, fillval = $FF;
}

7
libsrc/pce/clock.s
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@ -3,9 +3,9 @@
;
.export _clock
.constructor initclock, 24
.constructor initclock
.forceimport ticktock
.forceimport ticktock ; make sure that tickcount changes
.importzp sreg
.include "extzp.inc"
@ -20,6 +20,9 @@
rts
.endproc
; Make the process clock start at zero.
.segment "ONCE"
initclock:
lda #0

10
libsrc/pce/clrscr.s
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@ -1,3 +1,9 @@
;
; Clear (erase) the screen.
;
; Support the full 128- x 64-tile background.
;
.export _clrscr
.import plot
@ -15,9 +21,9 @@ _clrscr:
rowloop:
ldx #$80
colloop:
lda #' '
lda #' ' ; low byte of char. index
sta VDC_DATA_LO
lda #$02
lda #$02 ; background color, high nybble of char. index
sta VDC_DATA_HI
dex

12
libsrc/pce/color.s
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@ -12,17 +12,17 @@
.include "pce.inc"
.include "extzp.inc"
_bordercolor := return0
_bordercolor := return0 ; always black
_textcolor:
ldx CHARCOLOR ; get old value
sta CHARCOLOR ; set new value
ldx CHARCOLOR ; get old value
sta CHARCOLOR ; set new value
txa
rts
_bgcolor:
ldx BGCOLOR ; get old value
sta BGCOLOR ; set new value
ldx BGCOLOR ; get old value
sta BGCOLOR ; set new value
asl a
tay
@ -43,7 +43,7 @@ colors: .word ((0<<6)+(0<<3)+(0)) ; $0 black
.word ((7<<6)+(7<<3)+(7)) ; $1 white
.word ((0<<6)+(7<<3)+(0)) ; $2 red
.word ((7<<6)+(0<<3)+(7)) ; $3 cyan
.word ((0<<6)+(5<<3)+(7)) ; $4 violett
.word ((0<<6)+(5<<3)+(7)) ; $4 violet
.word ((7<<6)+(0<<3)+(0)) ; $5 green
.word ((0<<6)+(0<<3)+(7)) ; $6 blue
.word ((7<<6)+(7<<3)+(0)) ; $7 yellow

21
libsrc/pce/conio.s
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@ -28,7 +28,7 @@ set_palette:
ldx #0
@lp:
ldy #16
ldy #16 ; size of a pallette
@lp1:
lda colors,x
sta VCE_DATA_LO
@ -42,6 +42,8 @@ set_palette:
cpx #16 * 2
jne @lp
; Set background to black.
stz VCE_ADDR_LO
stz VCE_ADDR_HI
stz VCE_DATA_LO
@ -49,13 +51,18 @@ set_palette:
rts
;----------------------------------------------------------------------------
; The character tiles use only two colors from each pallette. Color zero
; comes from pallette zero; color one is different in each pallette. The
; color of a character is set by choosing one of the 16 pallettes.
conio_init:
; Load font
st0 #VDC_MAWR
st1 #<$2000
st2 #>$2000
; ptr to font data
; pointer to font data
lda #<font
sta ptr1
lda #>font
@ -76,7 +83,7 @@ conio_init:
sta tmp1
jsr copy
ldx #0
ldx #0 ; white on black
stx BGCOLOR
inx
stx CHARCOLOR
@ -101,11 +108,11 @@ lineloop:
adc #$00
sta ptr1+1
dex
bne lineloop ; next bitplane 0 byte
ldx #$08 ; fill bitplane 2/3 with 0
bne lineloop ; next bitplane-0 byte
ldx #$08 ; fill bitplanes 2 and 3 with 0
fillloop:
st1 #$00
st2 #$00
st1 #<$0000
st2 #>$0000
dex
bne fillloop ; next byte
dey

15
libsrc/pce/cputc.s
View File

@ -25,10 +25,10 @@ _cputc: cmp #$0D ; CR?
bne L1
lda #0
sta CURS_X
beq plot ; Recalculate pointers
beq plot ; Recalculate pointer
L1: cmp #$0A ; LF?
beq newline ; Recalculate pointers
beq newline ; Recalculate pointer
; Printable char of some sort
@ -50,23 +50,21 @@ L3: sty CURS_X
newline:
inc CURS_Y
; Set cursor position, calculate RAM pointers
; Set cursor position; calculate VRAM pointer.
plot: ldy CURS_X
ldx CURS_Y
clc
jmp PLOT ; Set the new cursor
; Write one character to the screen without doing anything else, return X
; position in Y
; Write one character to the screen without doing anything else.
putchar:
ora RVS ; Set revers bit
tax
st0 #VDC_MAWR ; Memory Adress Write
st0 #VDC_MAWR ; Memory Address Write
lda SCREEN_PTR
sta VDC_DATA_LO
@ -79,8 +77,7 @@ putchar:
txa
sta VDC_DATA_LO ; character
lda CHARCOLOR
lda CHARCOLOR ; pallette number
asl a
asl a
asl a

6
libsrc/pce/crt0.s
View File

@ -36,7 +36,7 @@ start: sei
csh ; Set high-speed CPU mode
nop
; Set up stack and memory mapping
; Set up stack and memory mapping.
ldx #$FF ; Stack top ($21FF)
txs
@ -74,7 +74,7 @@ start: sei
; Turn on background and VD interrupt/IRQ1
lda #$05
sta IRQ_MASK ; IRQ1=on
sta IRQ_MASK ; IRQ1 = on
; Copy the .data segment to RAM
tii __DATA_LOAD__, __DATA_RUN__, __DATA_SIZE__
@ -87,7 +87,7 @@ start: sei
lda #<(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
ldx #>(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
sta sp
stx sp + 1
stx sp+1
; Call module constructors
jsr initlib

3
libsrc/pce/ctype.s
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@ -6,7 +6,7 @@
.include "ctype.inc"
; The tables are readonly, put them into the rodata segment
; The tables are read-only; put them into the RODATA segment.
.rodata
@ -23,7 +23,6 @@
;
; * We save some code in the isxxx functions.
__ctype:
.repeat 2
.byte CT_CTRL ; 0/00 ___ctrl_@___

2
libsrc/pce/gotoxy.s
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@ -1,5 +1,5 @@
;
; void gotoxy (unsigned char x, unsigned char y);
; void __fastcall__ gotoxy (unsigned char x, unsigned char y);
;
.export gotoxy, _gotoxy

3
libsrc/pce/joy_stat_stddrv.s
View File

@ -7,8 +7,7 @@
;
.export _joy_static_stddrv
.import _pce_stdjoy_joy
.rodata
_joy_static_stddrv := _pce_stdjoy_joy

2
libsrc/pce/psg.s
View File

@ -5,7 +5,7 @@
.segment "ONCE"
psg_init:
clx
stz PSG_GLOBAL_PAN ; Clear global balance
stz PSG_GLOBAL_PAN ; Silence global balance
psg_clear_loop:
stx PSG_CHAN_SELECT ; Select channel

12
libsrc/pce/revers.s
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@ -1,7 +1,11 @@
;
; Ullrich von Bassewitz, 07.08.1998
;
; unsigned char revers (unsigned char onoff);
;
.export _revers
.include "pce.inc"
.include "extzp.inc"
.proc _revers
@ -18,9 +22,3 @@ L2: ldx #$00 ; Load high byte of result
tya ; Load low byte, set CC
rts
.endproc
;-------------------------------------------------------------------------------
; force the init constructor to be imported
.import initconio
conio_init = initconio

3
libsrc/pce/vdc.s
View File

@ -1,4 +1,3 @@
.export vdc_init
.include "pce.inc"
@ -15,7 +14,7 @@ vdc_init:
VREG $06, $0000 ; RCR
VREG $07, $0000 ; BXR
VREG $08, $0000 ; BYR
VREG $09, $0070 ; MAWR
VREG $09, $0070 ; MWR
VREG $0C, $1702 ; CRTC - VSR
VREG $0D, $00DF ; CRTC - VDS
VREG $0E, $000C ; CRTC - VDE

3
libsrc/pce/waitvsync.s
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@ -6,9 +6,8 @@
.export _waitvsync
.forceimport ticktock
.forceimport ticktock ; make sure that tickcount changes
.include "pce.inc"
.include "extzp.inc"
.proc _waitvsync