mirror of
https://github.com/cc65/cc65.git
synced 2025-01-12 17:30:50 +00:00
Added the remaining HuC6280 instructions
git-svn-id: svn://svn.cc65.org/cc65/trunk@3615 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
cuz
parent
0bdf6211bc
commit
d1ee736417
292
src/ca65/instr.c
292
src/ca65/instr.c
@ -63,23 +63,80 @@
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/*****************************************************************************/
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/* Data */
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/* Forwards */
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/*****************************************************************************/
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/* Forwards for handler functions */
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static void PutPCRel8 (const InsDesc* Ins);
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/* Handle branches with a 8 bit distance */
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static void PutPCRel16 (const InsDesc* Ins);
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/* Handle branches with an 16 bit distance and PER */
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static void PutBlockMove (const InsDesc* Ins);
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/* Handle the blockmove instructions (65816) */
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static void PutBlockTransfer (const InsDesc* Ins);
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/* Handle the block transfer instructions (HuC6280) */
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static void PutBitBranch (const InsDesc* Ins);
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/* Handle 65C02 branch on bit condition */
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static void PutREP (const InsDesc* Ins);
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/* Emit a REP instruction, track register sizes */
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static void PutSEP (const InsDesc* Ins);
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/* Emit a SEP instruction (65816), track register sizes */
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static void PutTAMn (const InsDesc* Ins);
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/* Emit a TAMn instruction (HuC6280). Since this is a two byte instruction with
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* implicit addressing mode, the opcode byte in the table is actually the
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* second operand byte. The TAM instruction is the more generic form, it takes
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* an immediate argument.
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*/
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static void PutTMA (const InsDesc* Ins);
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/* Emit a TMA instruction (HuC6280) with an immediate argument. Only one bit
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* in the argument byte may be set.
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*/
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static void PutTMAn (const InsDesc* Ins);
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/* Emit a TMAn instruction (HuC6280). Since this is a two byte instruction with
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* implicit addressing mode, the opcode byte in the table is actually the
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* second operand byte. The TAM instruction is the more generic form, it takes
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* an immediate argument.
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*/
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static void PutTST (const InsDesc* Ins);
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/* Emit a TST instruction (HuC6280). */
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static void PutJMP (const InsDesc* Ins);
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static void PutRTS (const InsDesc* Ins);
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/* Handle the jump instruction for the 6502. Problem is that these chips have
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* a bug: If the address crosses a page, the upper byte gets not corrected and
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* the instruction will fail. The PutJmp function will add a linker assertion
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* to check for this case and is otherwise identical to PutAll.
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*/
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static void PutRTS (const InsDesc* Ins attribute ((unused)));
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/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
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* the enclosing scope is FAR.
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*/
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static void PutAll (const InsDesc* Ins);
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/* Handle all other instructions */
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static void PutSweet16 (const InsDesc* Ins);
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/* Handle a generic sweet16 instruction */
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static void PutSweet16Branch (const InsDesc* Ins);
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/* Handle a sweet16 branch instruction */
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/*****************************************************************************/
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/* Data */
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/*****************************************************************************/
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@ -575,7 +632,7 @@ static const struct {
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/* Instruction table for the HuC6280 (the CPU used in the PC engine) */
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static const struct {
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unsigned Count;
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InsDesc Ins[107];
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InsDesc Ins[135];
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} InsTabHuC6280 = {
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sizeof (InsTabHuC6280.Ins) / sizeof (InsTabHuC6280.Ins[0]),
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{
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@ -607,6 +664,7 @@ static const struct {
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{ "BPL", 0x0020000, 0x10, 0, PutPCRel8 },
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{ "BRA", 0x0020000, 0x80, 0, PutPCRel8 },
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{ "BRK", 0x0000001, 0x00, 0, PutAll },
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{ "BSR", 0x0020000, 0x44, 0, PutPCRel8 },
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{ "BVC", 0x0020000, 0x50, 0, PutPCRel8 },
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{ "BVS", 0x0020000, 0x70, 0, PutPCRel8 },
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{ "CLA", 0x0000001, 0x62, 0, PutAll },
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@ -673,15 +731,42 @@ static const struct {
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{ "SMB5", 0x0000004, 0xD7, 1, PutAll },
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{ "SMB6", 0x0000004, 0xE7, 1, PutAll },
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{ "SMB7", 0x0000004, 0xF7, 1, PutAll },
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{ "ST0", 0x0800000, 0x03, 1, PutAll },
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{ "ST1", 0x0800000, 0x13, 1, PutAll },
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{ "ST2", 0x0800000, 0x23, 1, PutAll },
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{ "STA", 0x000A66C, 0x80, 0, PutAll },
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{ "STX", 0x000010c, 0x82, 1, PutAll },
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{ "STY", 0x000002c, 0x80, 1, PutAll },
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{ "STZ", 0x000006c, 0x04, 5, PutAll },
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{ "SXY", 0x0000001, 0x02, 0, PutAll },
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{ "TAI", 0x2000000, 0xf3, 0, PutBlockTransfer },
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{ "TAM", 0x0800000, 0x53, 1, PutAll },
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{ "TAM0", 0x0000001, 0x01, 0, PutTAMn},
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{ "TAM1", 0x0000001, 0x02, 0, PutTAMn},
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{ "TAM2", 0x0000001, 0x04, 0, PutTAMn},
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{ "TAM3", 0x0000001, 0x08, 0, PutTAMn},
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{ "TAM4", 0x0000001, 0x10, 0, PutTAMn},
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{ "TAM5", 0x0000001, 0x20, 0, PutTAMn},
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{ "TAM6", 0x0000001, 0x40, 0, PutTAMn},
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{ "TAM7", 0x0000001, 0x80, 0, PutTAMn},
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{ "TAX", 0x0000001, 0xaa, 0, PutAll },
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{ "TAY", 0x0000001, 0xa8, 0, PutAll },
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{ "TDD", 0x2000000, 0xc3, 0, PutBlockTransfer },
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{ "TIA", 0x2000000, 0xe3, 0, PutBlockTransfer },
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{ "TII", 0x2000000, 0x73, 0, PutBlockTransfer },
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{ "TIN", 0x2000000, 0xD3, 0, PutBlockTransfer },
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{ "TMA", 0x0800000, 0x43, 1, PutTMA },
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{ "TMA0", 0x0000001, 0x01, 0, PutTMAn},
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{ "TMA1", 0x0000001, 0x02, 0, PutTMAn},
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{ "TMA2", 0x0000001, 0x04, 0, PutTMAn},
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{ "TMA3", 0x0000001, 0x08, 0, PutTMAn},
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{ "TMA4", 0x0000001, 0x10, 0, PutTMAn},
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{ "TMA5", 0x0000001, 0x20, 0, PutTMAn},
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{ "TMA6", 0x0000001, 0x40, 0, PutTMAn},
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{ "TMA7", 0x0000001, 0x80, 0, PutTMAn},
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{ "TRB", 0x000000c, 0x10, 1, PutAll },
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{ "TSB", 0x000000c, 0x00, 1, PutAll },
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{ "TST", 0x000006c, 0x83, 9, PutTST },
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{ "TSX", 0x0000001, 0xba, 0, PutAll },
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{ "TXA", 0x0000001, 0x8a, 0, PutAll },
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{ "TXS", 0x0000001, 0x9a, 0, PutAll },
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@ -712,60 +797,66 @@ const InsTable* InsTab = (const InsTable*) &InsTab6502;
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/* Table to build the effective 65xx opcode from a base opcode and an
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* addressing mode.
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*/
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static unsigned char EATab[9][AM65I_COUNT] = {
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static unsigned char EATab[10][AM65I_COUNT] = {
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{ /* Table 0 */
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0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
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0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
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0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
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0x00
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},
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0x00, 0x00
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},
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{ /* Table 1 */
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0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
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0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 2 */
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0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 3 */
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0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 4 */
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0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 5 */
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0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 6 */
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0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
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0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 7 */
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0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 8 */
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0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
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0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
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0x00
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0x00, 0x00
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},
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{ /* Table 9 */
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0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00
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},
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};
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@ -783,31 +874,32 @@ static unsigned char Sweet16EATab[2][AMSW16I_COUNT] = {
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/* Table that encodes the additional bytes for each 65xx instruction */
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unsigned char ExtBytes[AM65I_COUNT] = {
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0, /* Implicit */
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0, /* Accu */
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1, /* Direct */
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2, /* Absolute */
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3, /* Absolute long */
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1, /* Direct,X */
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2, /* Absolute,X */
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3, /* Absolute long,X */
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1, /* Direct,Y */
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2, /* Absolute,Y */
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1, /* (Direct) */
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2, /* (Absolute) */
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1, /* [Direct] */
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1, /* (Direct),Y */
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1, /* [Direct],Y */
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1, /* (Direct,X) */
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2, /* (Absolute,X) */
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1, /* Relative short */
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2, /* Relative long */
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1, /* r,s */
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1, /* (r,s),y */
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1, /* Immidiate accu */
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1, /* Immidiate index */
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1, /* Immidiate byte */
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2 /* Blockmove */
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0, /* Implicit */
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0, /* Accu */
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1, /* Direct */
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2, /* Absolute */
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3, /* Absolute long */
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1, /* Direct,X */
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2, /* Absolute,X */
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3, /* Absolute long,X */
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1, /* Direct,Y */
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2, /* Absolute,Y */
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1, /* (Direct) */
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2, /* (Absolute) */
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1, /* [Direct] */
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1, /* (Direct),Y */
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1, /* [Direct],Y */
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1, /* (Direct,X) */
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2, /* (Absolute,X) */
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1, /* Relative short */
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2, /* Relative long */
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1, /* r,s */
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1, /* (r,s),y */
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1, /* Immidiate accu */
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1, /* Immidiate index */
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1, /* Immidiate byte */
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2, /* Blockmove (65816) */
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7, /* Block transfer (HuC6280) */
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};
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/* Table that encodes the additional bytes for each SWEET16 instruction */
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@ -1007,7 +1099,7 @@ static void PutPCRel16 (const InsDesc* Ins)
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static void PutBlockMove (const InsDesc* Ins)
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/* Handle the blockmove instructions */
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/* Handle the blockmove instructions (65816) */
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{
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Emit0 (Ins->BaseCode);
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EmitByte (Expression ());
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@ -1017,6 +1109,19 @@ static void PutBlockMove (const InsDesc* Ins)
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static void PutBlockTransfer (const InsDesc* Ins)
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/* Handle the block transfer instructions (HuC6280) */
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{
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Emit0 (Ins->BaseCode);
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EmitWord (Expression ());
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ConsumeComma ();
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EmitWord (Expression ());
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ConsumeComma ();
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EmitWord (Expression ());
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}
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static void PutBitBranch (const InsDesc* Ins)
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/* Handle 65C02 branch on bit condition */
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{
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@ -1042,7 +1147,7 @@ static void PutREP (const InsDesc* Ins)
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/* We had an error */
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Warning (1, "Cannot track processor status byte");
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} else {
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if (Val & 0x10) {
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if (Val & 0x10) {
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/* Index registers to 16 bit */
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ExtBytes[AM65I_IMM_INDEX] = 2;
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}
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@ -1057,7 +1162,7 @@ static void PutREP (const InsDesc* Ins)
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static void PutSEP (const InsDesc* Ins)
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/* Emit a SEP instruction, track register sizes */
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/* Emit a SEP instruction (65816), track register sizes */
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{
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/* Use the generic handler */
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long Val = PutImmed8 (Ins);
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@ -1071,12 +1176,12 @@ static void PutSEP (const InsDesc* Ins)
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Warning (1, "Cannot track processor status byte");
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} else {
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if (Val & 0x10) {
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/* Index registers to 8 bit */
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ExtBytes[AM65I_IMM_INDEX] = 1;
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/* Index registers to 8 bit */
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ExtBytes[AM65I_IMM_INDEX] = 1;
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}
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if (Val & 0x20) {
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/* Accu to 8 bit */
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ExtBytes[AM65I_IMM_ACCU] = 1;
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/* Accu to 8 bit */
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ExtBytes[AM65I_IMM_ACCU] = 1;
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}
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}
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}
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@ -1084,6 +1189,99 @@ static void PutSEP (const InsDesc* Ins)
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static void PutTAMn (const InsDesc* Ins)
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/* Emit a TAMn instruction (HuC6280). Since this is a two byte instruction with
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* implicit addressing mode, the opcode byte in the table is actually the
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* second operand byte. The TAM instruction is the more generic form, it takes
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* an immediate argument.
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*/
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{
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/* Emit the TAM opcode itself */
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Emit0 (0x53);
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/* Emit the argument, which is the opcode from the table */
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Emit0 (Ins->BaseCode);
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}
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static void PutTMA (const InsDesc* Ins)
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/* Emit a TMA instruction (HuC6280) with an immediate argument. Only one bit
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* in the argument byte may be set.
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*/
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{
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/* Use the generic handler */
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long Val = PutImmed8 (Ins);
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/* Check the range for Val. */
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if (Val < 0) {
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/* We had an error */
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Warning (1, "Cannot check argument of TMA instruction");
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} else {
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/* Make sure just one bit is set */
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if ((Val & (Val - 1)) != 0) {
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Error ("Argument to TAM must be a power of two");
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}
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}
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}
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static void PutTMAn (const InsDesc* Ins)
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/* Emit a TMAn instruction (HuC6280). Since this is a two byte instruction with
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* implicit addressing mode, the opcode byte in the table is actually the
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* second operand byte. The TAM instruction is the more generic form, it takes
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* an immediate argument.
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*/
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{
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/* Emit the TMA opcode itself */
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Emit0 (0x43);
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/* Emit the argument, which is the opcode from the table */
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Emit0 (Ins->BaseCode);
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}
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static void PutTST (const InsDesc* Ins)
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/* Emit a TST instruction (HuC6280). */
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{
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ExprNode* Arg1;
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EffAddr A;
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/* The first argument is always an immediate byte */
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if (Tok != TOK_HASH) {
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ErrorSkip ("Invalid addressing mode");
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return;
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}
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NextTok ();
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Arg1 = Expression ();
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/* Second argument follows */
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ConsumeComma ();
|
||||
|
||||
/* For the second argument, we use the standard function */
|
||||
if (EvalEA (Ins, &A)) {
|
||||
|
||||
/* No error, output code */
|
||||
Emit1 (A.Opcode, Arg1);
|
||||
|
||||
/* Check how many extension bytes are needed and output the instruction */
|
||||
switch (ExtBytes[A.AddrMode]) {
|
||||
|
||||
case 1:
|
||||
EmitByte (A.Expr);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
EmitWord (A.Expr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void PutJMP (const InsDesc* Ins)
|
||||
/* Handle the jump instruction for the 6502. Problem is that these chips have
|
||||
* a bug: If the address crosses a page, the upper byte gets not corrected and
|
||||
|
||||
@ -83,6 +83,7 @@
|
||||
#define AM65_IMM_IMPLICIT 0x00800000UL
|
||||
#define AM65_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT)
|
||||
#define AM65_BLOCKMOVE 0x01000000UL
|
||||
#define AM65_BLOCKXFER 0x02000000UL
|
||||
|
||||
/* Bitmask for all ZP operations that have correspondent ABS ops */
|
||||
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
|
||||
@ -93,7 +94,7 @@
|
||||
/* Bit numbers and count */
|
||||
#define AM65I_IMM_ACCU 21
|
||||
#define AM65I_IMM_INDEX 22
|
||||
#define AM65I_COUNT 25
|
||||
#define AM65I_COUNT 26
|
||||
|
||||
|
||||
|
||||
@ -101,16 +102,16 @@
|
||||
typedef struct InsDesc InsDesc;
|
||||
struct InsDesc {
|
||||
char Mnemonic[5];
|
||||
unsigned long AddrMode; /* Valid adressing modes */
|
||||
unsigned char BaseCode; /* Base opcode */
|
||||
unsigned char ExtCode; /* Number of ext code table */
|
||||
unsigned long AddrMode; /* Valid adressing modes */
|
||||
unsigned char BaseCode; /* Base opcode */
|
||||
unsigned char ExtCode; /* Number of ext code table */
|
||||
void (*Emit) (const InsDesc*);/* Handler function */
|
||||
};
|
||||
|
||||
/* An instruction table */
|
||||
/* An instruction table */
|
||||
typedef struct InsTable InsTable;
|
||||
struct InsTable {
|
||||
unsigned Count; /* Number of intstructions */
|
||||
unsigned Count; /* Number of intstructions */
|
||||
InsDesc Ins[1]; /* Varying length */
|
||||
};
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user