1
0
mirror of https://github.com/cc65/cc65.git synced 2024-06-07 07:29:33 +00:00

Apply faster popptr1 to functions and/or use register instead of stack to save accu.

This commit is contained in:
IrgendwerA8 2018-05-21 18:18:01 +02:00
parent 81b3c16c7e
commit d7da827be8
6 changed files with 30 additions and 30 deletions

View File

@ -6,8 +6,8 @@
.export tosumulax, tosmulax .export tosumulax, tosmulax
.import mul8x16, mul8x16a ; in mul8.s .import mul8x16, mul8x16a ; in mul8.s
.import popsreg .import popptr1
.importzp sreg, tmp1, ptr4 .importzp tmp1, ptr1, ptr4
;--------------------------------------------------------------------------- ;---------------------------------------------------------------------------
@ -19,12 +19,12 @@ tosumulax:
txa ; High byte zero txa ; High byte zero
beq @L3 ; Do 8x16 multiplication if high byte zero beq @L3 ; Do 8x16 multiplication if high byte zero
stx ptr4+1 ; Save right operand stx ptr4+1 ; Save right operand
jsr popsreg ; Get left operand jsr popptr1 ; Get left operand (Y=0 by popptr1)
; Do ptr4:ptr4+1 * sreg:sreg+1 --> AX ; Do ptr4:ptr4+1 * ptr1:ptr1+1 --> AX
lda #0 tya ; A = 0
ldx sreg+1 ; Get high byte into register for speed ldx ptr1+1 ; check if lhs is 8 bit only
beq @L4 ; -> we can do 8x16 after swap beq @L4 ; -> we can do 8x16 after swap
sta tmp1 sta tmp1
ldy #16 ; Number of bits ldy #16 ; Number of bits
@ -34,12 +34,12 @@ tosumulax:
@L0: bcc @L1 @L0: bcc @L1
clc clc
adc sreg adc ptr1
pha tax
txa ; hi byte of left op lda ptr1+1 ; hi byte of left op
adc tmp1 adc tmp1
sta tmp1 sta tmp1
pla txa
@L1: ror tmp1 @L1: ror tmp1
ror a ror a
@ -59,9 +59,9 @@ tosumulax:
; If the high byte of rhs is zero, swap the operands and use the 8x16 ; If the high byte of rhs is zero, swap the operands and use the 8x16
; routine. On entry, A and X are zero ; routine. On entry, A and X are zero
@L4: ldy sreg ; Save right operand (8 bit) @L4: ldy ptr1 ; Save right operand (8 bit)
ldx ptr4 ; Copy left 16 bit operand to right ldx ptr4 ; Copy left 16 bit operand to right
stx sreg stx ptr1
ldx ptr4+1 ; Don't store, this is done later ldx ptr4+1 ; Don't store, this is done later
sty ptr4 ; Copy low 8 bit of right op to left sty ptr4 ; Copy low 8 bit of right op to left
ldy #8 ldy #8

View File

@ -6,8 +6,8 @@
.export tosumula0, tosmula0 .export tosumula0, tosmula0
.export mul8x16, mul8x16a .export mul8x16, mul8x16a
.import popsreg .import popptr1
.importzp sreg, ptr4 .importzp ptr1, ptr4
;--------------------------------------------------------------------------- ;---------------------------------------------------------------------------
@ -16,11 +16,11 @@
tosmula0: tosmula0:
tosumula0: tosumula0:
sta ptr4 sta ptr4
mul8x16:jsr popsreg ; Get left operand mul8x16:jsr popptr1 ; Get left operand (Y=0 by popptr1)
lda #0 ; Clear byte 1 tya ; Clear byte 1
ldy #8 ; Number of bits ldy #8 ; Number of bits
ldx sreg+1 ; Get into register for speed ldx ptr1+1 ; check if lhs is 8 bit only
beq mul8x8 ; Do 8x8 multiplication if high byte zero beq mul8x8 ; Do 8x8 multiplication if high byte zero
mul8x16a: mul8x16a:
sta ptr4+1 ; Clear byte 2 sta ptr4+1 ; Clear byte 2
@ -29,12 +29,12 @@ mul8x16a:
@L0: bcc @L1 @L0: bcc @L1
clc clc
adc sreg adc ptr1
pha tax
txa ; hi byte of left op lda ptr1+1 ; hi byte of left op
adc ptr4+1 adc ptr4+1
sta ptr4+1 sta ptr4+1
pla txa
@L1: ror ptr4+1 @L1: ror ptr4+1
ror a ror a
@ -52,7 +52,7 @@ mul8x8:
lsr ptr4 ; Get first bit into carry lsr ptr4 ; Get first bit into carry
@L0: bcc @L1 @L0: bcc @L1
clc clc
adc sreg adc ptr1
@L1: ror @L1: ror
ror ptr4 ror ptr4
dey dey

View File

@ -15,11 +15,11 @@
rol ptr1+1 rol ptr1+1
clc clc
adc ptr1 adc ptr1
pha tay
txa txa
adc ptr1+1 adc ptr1+1
tax tax
pla tya
rts rts
.endproc .endproc

View File

@ -17,11 +17,11 @@
rol ptr1+1 rol ptr1+1
clc clc
adc ptr1 adc ptr1
pha tay
txa txa
adc ptr1+1 adc ptr1+1
tax tax
pla tya
rts rts
.endproc .endproc

View File

@ -20,12 +20,12 @@
rol ptr1+1 ; * 8 rol ptr1+1 ; * 8
sec sec
sbc ptr1 sbc ptr1
pha tay
txa txa
eor #$ff eor #$ff
adc ptr1+1 ; * (8 - 1) adc ptr1+1 ; * (8 - 1)
tax tax
pla tya
rts rts
.endproc .endproc

View File

@ -20,11 +20,11 @@
rol ptr1+1 ; * 8 rol ptr1+1 ; * 8
clc clc
adc ptr1 ; * (8+1) adc ptr1 ; * (8+1)
pha tay
txa txa
adc ptr1+1 adc ptr1+1
tax tax
pla tya
rts rts
.endproc .endproc