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Merge pull request #139 from mrdudz/addundocs

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Add missing undocs
This commit is contained in:
Oliver Schmidt 2014-11-20 14:55:07 +01:00
commit ff0bb9b11c
10 changed files with 651 additions and 49 deletions
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27
src/ca65/instr.c
View File

@ -215,7 +215,7 @@ static const struct {
/* Instruction table for the 6502 with illegal instructions */
static const struct {
unsigned Count;
InsDesc Ins[70];
InsDesc Ins[75];
} InsTab6502X = {
sizeof (InsTab6502X.Ins) / sizeof (InsTab6502X.Ins[0]),
{
@ -223,6 +223,7 @@ static const struct {
{ "ALR", 0x0800000, 0x4B, 0, PutAll }, /* X */
{ "ANC", 0x0800000, 0x0B, 0, PutAll }, /* X */
{ "AND", 0x080A26C, 0x20, 0, PutAll },
{ "ANE", 0x0800000, 0x8B, 0, PutAll }, /* X */
{ "ARR", 0x0800000, 0x6B, 0, PutAll }, /* X */
{ "ASL", 0x000006e, 0x02, 1, PutAll },
{ "AXS", 0x0800000, 0xCB, 0, PutAll }, /* X */
@ -256,12 +257,12 @@ static const struct {
{ "JMP", 0x0000808, 0x4c, 6, PutJMP },
{ "JSR", 0x0000008, 0x20, 7, PutAll },
{ "LAS", 0x0000200, 0xBB, 0, PutAll }, /* X */
{ "LAX", 0x000A30C, 0xA3, 1, PutAll }, /* X */
{ "LAX", 0x080A30C, 0xA3, 11, PutAll }, /* X */
{ "LDA", 0x080A26C, 0xa0, 0, PutAll },
{ "LDX", 0x080030C, 0xa2, 1, PutAll },
{ "LDY", 0x080006C, 0xa0, 1, PutAll },
{ "LSR", 0x000006F, 0x42, 1, PutAll },
{ "NOP", 0x0000001, 0xea, 0, PutAll },
{ "NOP", 0x080006D, 0x00, 10, PutAll }, /* X */
{ "ORA", 0x080A26C, 0x00, 0, PutAll },
{ "PHA", 0x0000001, 0x48, 0, PutAll },
{ "PHP", 0x0000001, 0x08, 0, PutAll },
@ -278,11 +279,15 @@ static const struct {
{ "SEC", 0x0000001, 0x38, 0, PutAll },
{ "SED", 0x0000001, 0xf8, 0, PutAll },
{ "SEI", 0x0000001, 0x78, 0, PutAll },
{ "SHA", 0x0002200, 0x93, 1, PutAll }, /* X */
{ "SHX", 0x0000200, 0x9e, 1, PutAll }, /* X */
{ "SHY", 0x0000040, 0x9c, 1, PutAll }, /* X */
{ "SLO", 0x000A26C, 0x03, 0, PutAll }, /* X */
{ "SRE", 0x000A26C, 0x43, 0, PutAll }, /* X */
{ "STA", 0x000A26C, 0x80, 0, PutAll },
{ "STX", 0x000010c, 0x82, 1, PutAll },
{ "STY", 0x000002c, 0x80, 1, PutAll },
{ "TAS", 0x0000200, 0x9b, 0, PutAll }, /* X */
{ "TAX", 0x0000001, 0xaa, 0, PutAll },
{ "TAY", 0x0000001, 0xa8, 0, PutAll },
{ "TSX", 0x0000001, 0xba, 0, PutAll },
@ -783,9 +788,9 @@ static const InsTable* InsTabs[CPU_COUNT] = {
const InsTable* InsTab = (const InsTable*) &InsTab6502;
/* Table to build the effective 65xx opcode from a base opcode and an
** addressing mode.
** addressing mode. (The value in the table is ORed with the base opcode)
*/
static unsigned char EATab[10][AM65I_COUNT] = {
static unsigned char EATab[12][AM65I_COUNT] = {
{ /* Table 0 */
0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
@ -846,6 +851,18 @@ static unsigned char EATab[10][AM65I_COUNT] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00
},
{ /* Table 10 (NOPs) */
0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00
},
{ /* Table 11 (LAX) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
0x00, 0x00, 0x80
},
};
/* Table to build the effective SWEET16 opcode from a base opcode and an

24
src/da65/opc6502x.c
View File

@ -51,7 +51,7 @@
const OpcDesc OpcTable_6502X[256] = {
{ "brk", 1, flNone, OH_Implicit }, /* $00 */
{ "ora", 2, flUseLabel, OH_DirectXIndirect }, /* $01 */
{ "kil", 1, flNone, OH_Implicit }, /* $02 */
{ "jam", 1, flNone, OH_Implicit }, /* $02 */
{ "slo", 2, flUseLabel, OH_DirectXIndirect }, /* $03 */
{ "nop", 2, flUseLabel, OH_Direct }, /* $04 */
{ "ora", 2, flUseLabel, OH_Direct }, /* $05 */
@ -67,7 +67,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "slo", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0f */
{ "bpl", 2, flLabel, OH_Relative }, /* $10 */
{ "ora", 2, flUseLabel, OH_DirectIndirectY }, /* $11 */
{ "kil", 1, flNone, OH_Implicit }, /* $12 */
{ "jam", 1, flNone, OH_Implicit }, /* $12 */
{ "slo", 2, flUseLabel, OH_DirectIndirectY }, /* $13 */
{ "nop", 2, flUseLabel, OH_DirectX }, /* $14 */
{ "ora", 2, flUseLabel, OH_DirectX }, /* $15 */
@ -83,7 +83,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "slo", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1f */
{ "jsr", 3, flLabel, OH_Absolute }, /* $20 */
{ "and", 2, flUseLabel, OH_DirectXIndirect }, /* $21 */
{ "kil", 1, flNone, OH_Implicit, }, /* $22 */
{ "jam", 1, flNone, OH_Implicit, }, /* $22 */
{ "rla", 2, flUseLabel, OH_DirectXIndirect }, /* $23 */
{ "bit", 2, flUseLabel, OH_Direct }, /* $24 */
{ "and", 2, flUseLabel, OH_Direct }, /* $25 */
@ -99,7 +99,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "rla", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2f */
{ "bmi", 2, flLabel, OH_Relative }, /* $30 */
{ "and", 2, flUseLabel, OH_DirectIndirectY }, /* $31 */
{ "kil", 1, flNone, OH_Implicit }, /* $32 */
{ "jam", 1, flNone, OH_Implicit }, /* $32 */
{ "rla", 2, flUseLabel, OH_DirectIndirectY }, /* $33 */
{ "nop", 2, flUseLabel, OH_DirectX }, /* $34 */
{ "and", 2, flUseLabel, OH_DirectX }, /* $35 */
@ -115,7 +115,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "rla", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3f */
{ "rti", 1, flNone, OH_Rts }, /* $40 */
{ "eor", 2, flUseLabel, OH_DirectXIndirect }, /* $41 */
{ "kil", 1, flNone, OH_Implicit }, /* $42 */
{ "jam", 1, flNone, OH_Implicit }, /* $42 */
{ "sre", 2, flUseLabel, OH_DirectXIndirect }, /* $43 */
{ "nop", 2, flUseLabel, OH_Direct }, /* $44 */
{ "eor", 2, flUseLabel, OH_Direct }, /* $45 */
@ -131,7 +131,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "sre", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4f */
{ "bvc", 2, flLabel, OH_Relative }, /* $50 */
{ "eor", 2, flUseLabel, OH_DirectIndirectY }, /* $51 */
{ "kil", 1, flNone, OH_Implicit }, /* $52 */
{ "jam", 1, flNone, OH_Implicit }, /* $52 */
{ "sre", 2, flUseLabel, OH_DirectIndirectY }, /* $53 */
{ "nop", 2, flUseLabel, OH_DirectX }, /* $54 */
{ "eor", 2, flUseLabel, OH_DirectX }, /* $55 */
@ -147,7 +147,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "sre", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5f */
{ "rts", 1, flNone, OH_Rts }, /* $60 */
{ "adc", 2, flUseLabel, OH_DirectXIndirect }, /* $61 */
{ "kil", 1, flNone, OH_Implicit }, /* $62 */
{ "jam", 1, flNone, OH_Implicit }, /* $62 */
{ "rra", 2, flUseLabel, OH_DirectXIndirect }, /* $63 */
{ "nop", 2, flUseLabel, OH_Direct }, /* $64 */
{ "adc", 2, flUseLabel, OH_Direct }, /* $65 */
@ -163,7 +163,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "rra", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6f */
{ "bvs", 2, flLabel, OH_Relative }, /* $70 */
{ "adc", 2, flUseLabel, OH_DirectIndirectY }, /* $71 */
{ "kil", 1, flNone, OH_Implicit }, /* $72 */
{ "jam", 1, flNone, OH_Implicit }, /* $72 */
{ "rra", 2, flUseLabel, OH_DirectIndirectY }, /* $73 */
{ "nop", 2, flUseLabel, OH_DirectX }, /* $74 */
{ "adc", 2, flUseLabel, OH_DirectX }, /* $75 */
@ -195,7 +195,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "sax", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8f */
{ "bcc", 2, flLabel, OH_Relative }, /* $90 */
{ "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */
{ "kil", 1, flNone, OH_Implicit }, /* $92 */
{ "jam", 1, flNone, OH_Implicit }, /* $92 */
{ "ahx", 2, flUseLabel, OH_DirectIndirectY }, /* $93 */
{ "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
{ "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
@ -227,7 +227,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "lax", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $af */
{ "bcs", 2, flLabel, OH_Relative }, /* $b0 */
{ "lda", 2, flUseLabel, OH_DirectIndirectY }, /* $b1 */
{ "kil", 1, flNone, OH_Implicit }, /* $b2 */
{ "jam", 1, flNone, OH_Implicit }, /* $b2 */
{ "lax", 2, flUseLabel, OH_DirectIndirectY }, /* $b3 */
{ "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */
{ "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */
@ -259,7 +259,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "dcp", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cf */
{ "bne", 2, flLabel, OH_Relative }, /* $d0 */
{ "cmp", 2, flUseLabel, OH_DirectIndirectY }, /* $d1 */
{ "kil", 1, flNone, OH_Implicit }, /* $d2 */
{ "jam", 1, flNone, OH_Implicit }, /* $d2 */
{ "dcp", 2, flUseLabel, OH_DirectIndirectY }, /* $d3 */
{ "nop", 2, flUseLabel, OH_DirectX }, /* $d4 */
{ "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */
@ -291,7 +291,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "isc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ef */
{ "beq", 2, flLabel, OH_Relative }, /* $f0 */
{ "sbc", 2, flUseLabel, OH_DirectIndirectY }, /* $f1 */
{ "kil", 1, flNone, OH_Implicit }, /* $f2 */
{ "jam", 1, flNone, OH_Implicit }, /* $f2 */
{ "isc", 2, flUseLabel, OH_DirectIndirectY }, /* $f3 */
{ "nop", 2, flUseLabel, OH_DirectX }, /* $f4 */
{ "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */

20
src/sim65/main.c
View File

@ -60,7 +60,8 @@
/* Name of program file */
const char* ProgramFile;
/* exit simulator after MaxCycles Cycles */
unsigned long MaxCycles = 0;
/*****************************************************************************/
/* Code */
@ -75,6 +76,7 @@ static void Usage (void)
" -h\t\t\tHelp (this text)\n"
" -v\t\t\tIncrease verbosity\n"
" -V\t\t\tPrint the simulator version number\n"
" -x <num>\t\tExit simulator after <num> cycles\n"
"\n"
"Long options:\n"
" --help\t\tHelp (this text)\n"
@ -111,7 +113,12 @@ static void OptVersion (const char* Opt attribute ((unused)),
fprintf (stderr, "sim65 V%s\n", GetVersionAsString ());
}
static void OptQuitXIns (const char* Opt attribute ((unused)),
const char* Arg attribute ((unused)))
/* quit after MaxCycles cycles */
{
MaxCycles = strtoul(Arg, NULL, 0);
}
static void ReadProgramFile (void)
/* Load program into memory */
@ -197,6 +204,10 @@ int main (int argc, char* argv[])
OptVersion (Arg, 0);
break;
case 'x':
OptQuitXIns (Arg, GetArg (&I, 2));
break;
default:
UnknownOption (Arg);
break;
@ -225,6 +236,11 @@ int main (int argc, char* argv[])
while (1) {
ExecuteInsn ();
if (MaxCycles && (GetCycles () >= MaxCycles)) {
Error ("Maximum number of cycles reached.");
exit (-99); /* do not ues EXIT_FAILURE to avoid conflicts with the
same value being used in a test program */
}
}
/* Return an apropriate exit code */

6
testcode/assembler/.gitignore vendored Normal file
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@ -0,0 +1,6 @@
chkillegal.bin
chklegal.bin
chkall.bin
legal.o
illegal.o
all.o

25
testcode/assembler/Makefile Normal file
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@ -0,0 +1,25 @@
all: chklegal.bin chkillegal.bin chkall.bin
@#
.PHONY: chklegal.bin chkillegal.bin chkall.bin
chklegal.bin: legal.s
../../bin/cl65 --target none --cpu 6502X -o chklegal.bin legal.s
diff -q legal.ref chklegal.bin || hex chklegal.bin
chkillegal.bin: illegal.s
../../bin/cl65 --target none --cpu 6502X -o chkillegal.bin illegal.s
diff -q illegal.ref chkillegal.bin || hex chkillegal.bin
chkall.bin: all.s
../../bin/cl65 --target none --cpu 6502X -o chkall.bin all.s
ref: legal.s illegal.s
../../bin/cl65 --target none --cpu 6502X -o legal.ref legal.s
../../bin/cl65 --target none --cpu 6502X -o illegal.ref illegal.s
clean:
rm -f legal.o chklegal.bin
rm -f illegal.o chkillegal.bin
rm -f all.o chkall.bin

260
testcode/assembler/all.s Normal file
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@ -0,0 +1,260 @@
.setcpu "6502X"
; all legal and illegal opcodes as they would be disassembled by da65
; note that this would not assemble into the exact same binary
brk ; 00
ora ($12,x) ; 01 12
jam ; 02
slo ($12,x) ; 03 12
nop $12 ; 04 12
ora $12 ; 05 12
asl $12 ; 06 12
slo $12 ; 07 12
php ; 08
ora #$12 ; 09 12
asl a ; 0a
anc #$12 ; 0b 12
nop $1234 ; 0c 34 12
ora $1234 ; 0d 34 12
asl $1234 ; 0e 34 12
slo $1234 ; 0f 34 12
bpl *+$14 ; 10 12
ora ($12),y ; 11 12
jam ; 12
slo ($12),y ; 13 12
nop $12,x ; 14 12
ora $12,x ; 15 12
asl $12,x ; 16 12
slo $12,x ; 17 12
clc ; 18
ora $1234,y ; 19 34 12
nop ; 1a
slo $1234,y ; 1b 34 12
nop $1234,x ; 1c 34 12
ora $1234,x ; 1d 34 12
asl $1234,x ; 1e 34 12
slo $1234,x ; 1f 34 12
jsr $1234 ; 20 34 12
and ($12,x) ; 21 12
jam ; 22
rla ($12,x) ; 23 12
bit $12 ; 24 12
and $12 ; 25 12
rol $12 ; 26 12
rla $12 ; 27 12
plp ; 28
and #$12 ; 29 12
rol a ; 2a
anc #$12 ; 2b 12
bit $1234 ; 2c 34 12
and $1234 ; 2d 34 12
rol $1234 ; 2e 34 12
rla $1234 ; 2f 34 12
bmi *+$14 ; 30 12
and ($12),y ; 31 12
jam ; 32
rla ($12),y ; 33 12
nop $12,x ; 34 12
and $12,x ; 35 12
rol $12,x ; 36 12
rla $12,x ; 37 12
sec ; 38
and $1234,y ; 39 34 12
nop ; 3a
rla $1234,y ; 3b 34 12
nop $1234,x ; 3c 34 12
and $1234,x ; 3d 34 12
rol $1234,x ; 3e 34 12
rla $1234,x ; 3f 34 12
rti ; 40
eor ($12,x) ; 41 12
jam ; 42
sre ($12,x) ; 43 12
nop $12 ; 44 12
eor $12 ; 45 12
lsr $12 ; 46 12
sre $12 ; 47 12
pha ; 48
eor #$12 ; 49 12
lsr a ; 4a
alr #$12 ; 4b 12
jmp $1234 ; 4c 34 12
eor $1234 ; 4d 34 12
lsr $1234 ; 4e 34 12
sre $1234 ; 4f 34 12
bvc *+$14 ; 50 12
eor ($12),y ; 51 12
jam ; 52
sre ($12),y ; 53 12
nop $12,x ; 54 12
eor $12,x ; 55 12
lsr $12,x ; 56 12
sre $12,x ; 57 12
cli ; 58
eor $1234,y ; 59 34 12
nop ; 5a
sre $1234,y ; 5b 34 12
nop $1234,x ; 5c 34 12
eor $1234,x ; 5d 34 12
lsr $1234,x ; 5e 34 12
sre $1234,x ; 5f 34 12
rts ; 60
adc ($12,x) ; 61 12
jam ; 62
rra ($12,x) ; 63 12
nop $12 ; 64 12
adc $12 ; 65 12
ror $12 ; 66 12
rra $12 ; 67 12
pla ; 68
adc #$12 ; 69 12
ror a ; 6a
arr #$12 ; 6b 12
jmp ($1234) ; 6c 34 12
adc $1234 ; 6d 34 12
ror $1234 ; 6e 34 12
rra $1234 ; 6f 34 12
bvs *+$14 ; 70 12
adc ($12),y ; 71 12
jam ; 72
rra ($12),y ; 73 12
nop $12,x ; 74 12
adc $12,x ; 75 12
ror $12,x ; 76 12
rra $12,x ; 77 12
sei ; 78
adc $1234,y ; 79 34 12
nop ; 7a
rra $1234,y ; 7b 34 12
nop $1234,x ; 7c 34 12
adc $1234,x ; 7d 34 12
ror $1234,x ; 7e 34 12
rra $1234,x ; 7f 34 12
nop #$12 ; 80 12
sta ($12,x) ; 81 12
nop #$12 ; 82 12
sax ($12,x) ; 83 12
sty $12 ; 84 12
sta $12 ; 85 12
stx $12 ; 86 12
sax $12 ; 87 12
dey ; 88
nop #$12 ; 89 12
txa ; 8a
ane #$12 ; 8b 12
sty $1234 ; 8c 34 12
sta $1234 ; 8d 34 12
stx $1234 ; 8e 34 12
sax $1234 ; 8f 34 12
bcc *+$14 ; 90 12
sta ($12),y ; 91 12
jam ; 92
sha ($12),y ; 93 12
sty $12,x ; 94 12
sta $12,x ; 95 12
stx $12,y ; 96 12
sax $12,y ; 97 12
tya ; 98
sta $1234,y ; 99 34 12
txs ; 9a
tas $1234,y ; 9b 34 12
shy $1234,x ; 9c 34 12
sta $1234,x ; 9d 34 12
shx $1234,y ; 9e 34 12
sha $1234,y ; 9f 34 12
ldy #$12 ; a0 12
lda ($12,x) ; a1 12
ldx #$12 ; a2 12
lax ($12,x) ; a3 12
ldy $12 ; a4 12
lda $12 ; a5 12
ldx $12 ; a6 12
lax $12 ; a7 12
tay ; a8
lda #$12 ; a9 12
tax ; aa
lax #$12 ; ab 12
ldy $1234 ; ac 34 12
lda $1234 ; ad 34 12
ldx $1234 ; ae 34 12
lax $1234 ; af 34 12
bcs *+$14 ; b0 12
lda ($12),y ; b1 12
jam ; b2
lax ($12),y ; b3 12
ldy $12,x ; b4 12
lda $12,x ; b5 12
ldx $12,y ; b6 12
lax $12,y ; b7 12
clv ; b8
lda $1234,y ; b9 34 12
tsx ; ba
las $1234,y ; bb 34 12
ldy $1234,x ; bc 34 12
lda $1234,x ; bd 34 12
ldx $1234,y ; be 34 12
lax $1234,y ; bf 34 12
cpy #$12 ; c0 12
cmp ($12,x) ; c1 12
nop #$12 ; c2 12
dcp ($12,x) ; c3 12
cpy $12 ; c4 12
cmp $12 ; c5 12
dec $12 ; c6 12
dcp $12 ; c7 12
iny ; c8
cmp #$12 ; c9 12
dex ; ca
axs #$12 ; cb 12
cpy $1234 ; cc 34 12
cmp $1234 ; cd 34 12
dec $1234 ; ce 34 12
dcp $1234 ; cf 34 12
bne *+$14 ; d0 12
cmp ($12),y ; d1 12
jam ; d2
dcp ($12),y ; d3 12
nop $12,x ; d4 12
cmp $12,x ; d5 12
dec $12,x ; d6 12
dcp $12,x ; d7 12
cld ; d8
cmp $1234,y ; d9 34 12
nop ; da
dcp $1234,y ; db 34 12
nop $1234,x ; dc 34 12
cmp $1234,x ; dd 34 12
dec $1234,x ; de 34 12
dcp $1234,x ; df 34 12
cpx #$12 ; e0 12
sbc ($12,x) ; e1 12
nop #$12 ; e2 12
isc ($12,x) ; e3 12
cpx $12 ; e4 12
sbc $12 ; e5 12
inc $12 ; e6 12
isc $12 ; e7 12
inx ; e8
sbc #$12 ; e9 12
nop ; ea
sbc #$12 ; eb 12
cpx $1234 ; ec 34 12
sbc $1234 ; ed 34 12
inc $1234 ; ee 34 12
isc $1234 ; ef 34 12
beq *+$14 ; f0 12
sbc ($12),y ; f1 12
jam ; f2
isc ($12),y ; f3 12
nop $12,x ; f4 12
sbc $12,x ; f5 12
inc $12,x ; f6 12
isc $12,x ; f7 12
sed ; f8
sbc $1234,y ; f9 34 12
isc $1234,y ; fb 34 12
nop $1234,x ; fc 34 12
sbc $1234,x ; fd 34 12
inc $1234,x ; fe 34 12
isc $1234,x ; ff 34 12

1
testcode/assembler/illegal.ref Normal file
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@ -0,0 +1 @@
444'/4?4;4#73O4_4[4GCWSo44{4gcwsΟ4ί4Ϋ4ΗΓΧΣο4<12>4ϋ4ηγχσ<12>4‡ƒ—―4Ώ4§£³· kKΛ 44€“<12>4<12>4<12>4›4»4«‹

152
testcode/assembler/illegal.s
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@ -1,43 +1,135 @@
.setcpu "6502X"
; all so called "illegal" opcodes. duplicated (functionally identical) ones
; are commented out
.macro test opc
; first all totally stable undocs:
opc $00
opc $00,x
opc ($00,x)
opc ($00),y
opc $1234
opc $1234,x
opc $1234,y
slo $12 ; 07 12
slo $1234 ; 0f 34 12
slo $1234,x ; 1f 34 12
slo $1234,y ; 1b 34 12
slo ($12,x) ; 03 12
slo $12,x ; 17 12
slo ($12),y ; 13 12
.endmacro
rla $12 ; 27 12
rla $1234 ; 2f 34 12
rla $1234,x ; 3f 34 12
rla $1234,y ; 3b 34 12
rla ($12,x) ; 23 12
rla $12,x ; 37 12
rla ($12),y ; 33 12
sre $1234 ; 4f 34 12
sre $1234,x ; 5f 34 12
sre $1234,y ; 5b 34 12
sre $12 ; 47 12
sre ($12,x) ; 43 12
sre $12,x ; 57 12
sre ($12),y ; 53 12
test slo
test rla
test sre
test rra
test dcp
test isc
rra $1234 ; 6f 34 12
rra $1234,x ; 7f 34 12
rra $1234,y ; 7b 34 12
rra $12 ; 67 12
rra ($12,x) ; 63 12
rra $12,x ; 77 12
rra ($12),y ; 73 12
sax $00
sax $00,y
sax ($00,x)
sax $1234
dcp $1234 ; cf 34 12
dcp $1234,x ; df 34 12
dcp $1234,y ; db 34 12
dcp $12 ; c7 12
dcp ($12,x) ; c3 12
dcp $12,x ; d7 12
dcp ($12),y ; d3 12
lax $00
lax $00,y
lax ($00,x)
lax ($00),y
lax $1234
lax $1234,y
isc $1234 ; ef 34 12
isc $1234,x ; ff 34 12
isc $1234,y ; fb 34 12
isc $12 ; e7 12
isc ($12,x) ; e3 12
isc $12,x ; f7 12
isc ($12),y ; f3 12
anc #$55
alr #$55
arr #$55
axs #$55
sax $1234 ; 8f 34 12
sax $12 ; 87 12
sax ($12,x) ; 83 12
sax $12,y ; 97 12
las $1234,y
lax $1234 ; af 34 12
lax $1234,y ; bf 34 12
lax $12 ; a7 12
lax ($12,x) ; a3 12
lax ($12),y ; b3 12
lax $12,y ; b7 12
anc #$12 ; 0b 12
;anc #$12 ; 2b 12
arr #$12 ; 6b 12
alr #$12 ; 4b 12
axs #$12 ; cb 12
nop $1234 ; 0c 34 12
nop $1234,x ; 1c 34 12
nop $12 ; 04 12
nop $12,x ; 14 12
nop #$12 ; 80 12
;nop $1234,x ; 3c 34 12
;nop $1234,x ; 5c 34 12
;nop $1234,x ; 7c 34 12
;nop $1234,x ; dc 34 12
;nop $1234,x ; fc 34 12
;nop $12 ; 44 12
;nop $12 ; 64 12
;nop #$12 ; 82 12
;nop #$12 ; 89 12
;nop #$12 ; c2 12
;nop #$12 ; e2 12
;nop $12,x ; 34 12
;nop $12,x ; 54 12
;nop $12,x ; 74 12
;nop $12,x ; d4 12
;nop $12,x ; f4 12
;nop ; 1a
;nop ; 3a
;nop ; 5a
;nop ; 7a
;nop ; da
jam ; 02
;jam ; 12
;jam ; 22
;jam ; 32
;jam ; 42
;jam ; 52
;jam ; 62
;jam ; 72
;jam ; 92
;jam ; b2
;jam ; d2
;jam ; f2
;sbc #$12 ; eb 12
; the so-called "unstable" ones:
sha ($12),y ; 93 12
sha $1234,y ; 9f 34 12
shx $1234,y ; 9e 34 12
shy $1234,x ; 9c 34 12
tas $1234,y ; 9b 34 12
las $1234,y ; bb 34 12
; the two so-called "highly unstable" ones:
lax #$12 ; ab 12
ane #$12 ; 8b 12

BIN
testcode/assembler/legal.ref Normal file
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185
testcode/assembler/legal.s Normal file
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@ -0,0 +1,185 @@
.setcpu "6502"
adc $1234 ; 6d 34 12
adc $1234,x ; 7d 34 12
adc $1234,y ; 79 34 12
adc $12 ; 65 12
adc #$12 ; 69 12
adc ($12,x) ; 61 12
adc $12,x ; 75 12
adc ($12),y ; 71 12
and $12 ; 25 12
and #$12 ; 29 12
and $1234 ; 2d 34 12
and $1234,x ; 3d 34 12
and $1234,y ; 39 34 12
and ($12,x) ; 21 12
and $12,x ; 35 12
and ($12),y ; 31 12
asl $12 ; 06 12
asl $1234 ; 0e 34 12
asl $1234,x ; 1e 34 12
asl $12,x ; 16 12
asl a ; 0a
bcc *+$14 ; 90 12
bcs *+$14 ; b0 12
beq *+$14 ; f0 12
bmi *+$14 ; 30 12
bne *+$14 ; d0 12
bpl *+$14 ; 10 12
bvc *+$14 ; 50 12
bvs *+$14 ; 70 12
bit $12 ; 24 12
bit $1234 ; 2c 34 12
brk ; 00
clc ; 18
cld ; d8
cli ; 58
clv ; b8
cmp $1234 ; cd 34 12
cmp $1234,x ; dd 34 12
cmp $1234,y ; d9 34 12
cmp $12 ; c5 12
cmp #$12 ; c9 12
cmp ($12,x) ; c1 12
cmp $12,x ; d5 12
cmp ($12),y ; d1 12
cpx $1234 ; ec 34 12
cpx #$12 ; e0 12
cpx $12 ; e4 12
cpy $1234 ; cc 34 12
cpy #$12 ; c0 12
cpy $12 ; c4 12
dec $1234 ; ce 34 12
dec $1234,x ; de 34 12
dec $12 ; c6 12
dec $12,x ; d6 12
dex ; ca
dey ; 88
eor $1234 ; 4d 34 12
eor $1234,x ; 5d 34 12
eor $1234,y ; 59 34 12
eor $12 ; 45 12
eor #$12 ; 49 12
eor ($12,x) ; 41 12
eor $12,x ; 55 12
eor ($12),y ; 51 12
inc $1234 ; ee 34 12
inc $1234,x ; fe 34 12
inc $12 ; e6 12
inc $12,x ; f6 12
inx ; e8
iny ; c8
jmp $1234 ; 4c 34 12
jmp ($1234) ; 6c 34 12
jsr $1234 ; 20 34 12
lda $1234 ; ad 34 12
lda $1234,x ; bd 34 12
lda $1234,y ; b9 34 12
lda $12 ; a5 12
lda #$12 ; a9 12
lda ($12,x) ; a1 12
lda $12,x ; b5 12
lda ($12),y ; b1 12
ldx $1234 ; ae 34 12
ldx $1234,y ; be 34 12
ldx #$12 ; a2 12
ldx $12 ; a6 12
ldx $12,y ; b6 12
ldy $1234 ; ac 34 12
ldy $1234,x ; bc 34 12
ldy #$12 ; a0 12
ldy $12 ; a4 12
ldy $12,x ; b4 12
lsr $1234 ; 4e 34 12
lsr $1234,x ; 5e 34 12
lsr $12 ; 46 12
lsr $12,x ; 56 12
lsr a ; 4a
nop ; ea
ora $12 ; 05 12
ora #$12 ; 09 12
ora $1234 ; 0d 34 12
ora $1234,x ; 1d 34 12
ora $1234,y ; 19 34 12
ora ($12,x) ; 01 12
ora $12,x ; 15 12
ora ($12),y ; 11 12
pha ; 48
php ; 08
pla ; 68
plp ; 28
rol $12 ; 26 12
rol $1234 ; 2e 34 12
rol $1234,x ; 3e 34 12
rol $12,x ; 36 12
rol a ; 2a
ror $1234 ; 6e 34 12
ror $1234,x ; 7e 34 12
ror $12 ; 66 12
ror $12,x ; 76 12
ror a ; 6a
rti ; 40
rts ; 60
sbc $1234 ; ed 34 12
sbc $1234,x ; fd 34 12
sbc $1234,y ; f9 34 12
sbc $12 ; e5 12
sbc #$12 ; e9 12
sbc ($12,x) ; e1 12
sbc $12,x ; f5 12
sbc ($12),y ; f1 12
sec ; 38
sed ; f8
sei ; 78
sta $1234 ; 8d 34 12
sta $1234,x ; 9d 34 12
sta $1234,y ; 99 34 12
sta $12 ; 85 12
sta ($12,x) ; 81 12
sta $12,x ; 95 12
sta ($12),y ; 91 12
stx $1234 ; 8e 34 12
stx $12 ; 86 12
stx $12,y ; 96 12
sty $1234 ; 8c 34 12
sty $12 ; 84 12
sty $12,x ; 94 12
tax ; aa
tay ; a8
tsx ; ba
txa ; 8a
txs ; 9a
tya ; 98