mirror of https://github.com/cc65/cc65.git
184 lines
7.6 KiB
C
184 lines
7.6 KiB
C
/*****************************************************************************/
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/* */
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/* instr.h */
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/* */
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/* Instruction encoding for the ca65 macroassembler */
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/* */
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/* */
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/* */
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/* (C) 1998-2012, Ullrich von Bassewitz */
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/* Roemerstrasse 52 */
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/* D-70794 Filderstadt */
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/* EMail: uz@cc65.org */
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/* */
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/* */
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/* This software is provided 'as-is', without any expressed or implied */
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/* warranty. In no event will the authors be held liable for any damages */
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/* arising from the use of this software. */
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/* */
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/* Permission is granted to anyone to use this software for any purpose, */
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/* including commercial applications, and to alter it and redistribute it */
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/* freely, subject to the following restrictions: */
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/* */
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/* 1. The origin of this software must not be misrepresented; you must not */
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/* claim that you wrote the original software. If you use this software */
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/* in a product, an acknowledgment in the product documentation would be */
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/* appreciated but is not required. */
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/* 2. Altered source versions must be plainly marked as such, and must not */
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/* be misrepresented as being the original software. */
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/* 3. This notice may not be removed or altered from any source */
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/* distribution. */
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/* */
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/*****************************************************************************/
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#ifndef INSTR_H
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#define INSTR_H
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/* common */
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#include "cpu.h"
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#include "strbuf.h"
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/*****************************************************************************/
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/* Data for 6502 and successors */
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/*****************************************************************************/
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/* Constants for the addressing mode. If an opcode is available in zero page
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** and absolut adressing mode, both bits are set. When checking for valid
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** modes, the zeropage bit is checked first. Similar, the implicit bit is set
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** on accu adressing modes, so the 'A' for accu adressing is not needed (but
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** may be specified).
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** When assembling for the 6502 or 65C02, all addressing modes that are not
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** available on these CPUs are removed before doing any checks.
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*/
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#define AM65_IMPLICIT 0x00000003UL
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#define AM65_ACCU 0x00000002UL
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#define AM65_DIR 0x00000004UL
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#define AM65_ABS 0x00000008UL
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#define AM65_ABS_LONG 0x00000010UL
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#define AM65_DIR_X 0x00000020UL
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#define AM65_ABS_X 0x00000040UL
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#define AM65_ABS_LONG_X 0x00000080UL
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#define AM65_DIR_Y 0x00000100UL
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#define AM65_ABS_Y 0x00000200UL
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#define AM65_DIR_IND 0x00000400UL
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#define AM65_ABS_IND 0x00000800UL
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#define AM65_DIR_IND_LONG 0x00001000UL
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#define AM65_DIR_IND_Y 0x00002000UL
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#define AM65_DIR_IND_LONG_Y 0x00004000UL
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#define AM65_DIR_X_IND 0x00008000UL
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#define AM65_ABS_X_IND 0x00010000UL
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#define AM65_REL 0x00020000UL
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#define AM65_REL_LONG 0x00040000UL
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#define AM65_STACK_REL 0x00080000UL
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#define AM65_STACK_REL_IND_Y 0x00100000UL
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#define AM65_IMM_ACCU 0x00200000UL
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#define AM65_IMM_INDEX 0x00400000UL
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#define AM65_IMM_IMPLICIT 0x00800000UL
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#define AM65_BLOCKMOVE 0x01000000UL
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#define AM65_BLOCKXFER 0x02000000UL
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#define AM65_ABS_IND_LONG 0x04000000UL
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#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
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/* Bitmask for all ZP operations that have correspondent ABS ops */
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#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
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/* Bitmask for all ABS operations that have correspondent FAR ops */
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#define AM65_SET_ABS (AM65_ABS | AM65_ABS_X)
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/* Bitmask for all ZP operations */
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#define AM65_ALL_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
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/* Bitmask for all ABS operations */
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#define AM65_ALL_ABS (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND)
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/* Bitmask for all FAR operations */
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#define AM65_ALL_FAR (AM65_ABS_LONG | AM65_ABS_LONG_X)
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/* Bitmask for all immediate operations */
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#define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
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/* Bit numbers and count */
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#define AM65I_IMM_ACCU 21
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#define AM65I_IMM_INDEX 22
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#define AM65I_IMM_IMPLICIT 23
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#define AM65I_IMM_IMPLICIT_WORD 27
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#define AM65I_COUNT 28
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/* Description for one instruction */
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typedef struct InsDesc InsDesc;
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struct InsDesc {
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char Mnemonic[5];
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unsigned long AddrMode; /* Valid adressing modes */
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unsigned char BaseCode; /* Base opcode */
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unsigned char ExtCode; /* Number of ext code table */
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void (*Emit) (const InsDesc*);/* Handler function */
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};
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/* An instruction table */
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typedef struct InsTable InsTable;
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struct InsTable {
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unsigned Count; /* Number of intstructions */
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InsDesc Ins[1]; /* Varying length */
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};
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/* The instruction table for the currently active CPU */
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extern const InsTable* InsTab;
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/* Table that encodes the additional bytes for each instruction */
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extern unsigned char ExtBytes[AM65I_COUNT];
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/*****************************************************************************/
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/* Data for the SWEET16 pseudo CPU */
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/*****************************************************************************/
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/* SWEET16 addressing modes */
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#define AMSW16_IMP 0x0001 /* Implicit */
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#define AMSW16_BRA 0x0002 /* A branch */
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#define AMSW16_IMM 0x0004 /* Immediate */
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#define AMSW16_IND 0x0008 /* Indirect */
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#define AMSW16_REG 0x0010 /* Register */
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#define AMSW16I_COUNT 5 /* Number of addressing modes */
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/*****************************************************************************/
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/* Code */
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/*****************************************************************************/
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void SetCPU (cpu_t NewCPU);
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/* Set a new CPU */
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cpu_t GetCPU (void);
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/* Return the current CPU */
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int FindInstruction (const StrBuf* Ident);
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/* Check if Ident is a valid mnemonic. If so, return the index in the
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** instruction table. If not, return -1.
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*/
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void HandleInstruction (unsigned Index);
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/* Handle the mnemonic with the given index */
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/* End of instr.h */
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#endif
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