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158 lines
5.2 KiB
ArmAsm
158 lines
5.2 KiB
ArmAsm
;
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; Ullrich von Bassewitz, 02.04.1999
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;
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; unsigned char getcpu (void);
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;
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.export _getcpu
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; ---------------------------------------------------------------------------
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; Subroutine to detect an 816. Returns
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;
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; - carry clear and 0 in A for a NMOS 6502 CPU
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; - carry set and 1 in A for a 65C02
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; - carry set and 2 in A for a 65816
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; - carry set and 3 in A for a 4510
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; - carry set and 4 in A for a 65SC02
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; - carry set and 5 in A for a 65CE02
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; - carry set and 6 in A for a HuC6280
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; - carry clear and 7 in A for a 2a03/2a07
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; - carry set and 8 in A for a 45GS02
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;
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; This function uses a $1A opcode which is a INA on the 816 and ignored
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; (interpreted as a NOP) on a NMOS 6502. There are several CMOS versions
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; of the 6502, but all of them interpret unknown opcodes as NOP so this is
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; just what we want.
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.p816 ; Enable 65816 instructions
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_getcpu:
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lda #0
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inc a ; .byte $1A ; nop on nmos, inc on every cmos
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cmp #1
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bcc @IsNMOS
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; This is at least a 65C02, check for a 65CE02/4510
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.byte $42,$EA ; neg on 65CE02/4510, nop #$EA on 65C02, wdm $EA on 65816
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cmp #1
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beq @HasINCA
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; This is at least a 65CE02, check for 4510
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lda #5 ; CPU_65CE02 constant
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ldx #0 ; to make sure MAP doesn't do anything, the upper nybl of X and Z must be clear
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.byte $5C ; map on 4510, aug on 65CE02 (acts like 4 byte nop)
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lda #3 ; CPU_4510 constant
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nop
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cmp #5
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beq @LoadXAndReturn
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; It is either a 4510 (C65) or a 45GS02 (MEGA65)
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; 45GS02 supports 32-bit ZP indirect, so use that to check CPU type
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; without requiring a functioning MEGA65 hypervisor.
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; We setup a read of $200FF, then store a different value in $00FF
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; and then re-read $200FF to see if it is unchanged.
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; Save the 32-bit ZP pointer and data byte
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ldx #4
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@L10: lda $fb,x
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sta @GetCPUTemp,x
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dex
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bpl @L10
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; Setup 32-bit pointer to $000200FF
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lda #$ff
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sta $fb
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lda #$00
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sta $fc
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sta $fe
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lda #$02
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sta $fd
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; Prefixing LDA ($nn),Z with a NOP uses 32-bit ZP pointer on 45GS02,
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; but normal 16-bit ZP pointer on 4510
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; (We assume Z=$00, which will be the normal case)
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nop ; prefix to tell next instruction to be 32-bit ZP
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.byte $b2,$fb ; LDA ($nn),Z
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eor #$ff ; change the value
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sta $ff ; store in $FF
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; now try again to load it: If the same, then 45GS02, as $200FF is unchanged
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nop ; prefix to tell next instruction to be 32-bit ZP
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.byte $b2,$fb ; LDA ($nn),Z
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cmp $ff ; does the loaded value match what is in $FF?
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beq @Is4510 ; matches, so must be a 4510 = C65
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bne @Is45GS02 ; $200FF and $FF have different values, so must be a MEGA65 45GS02
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@Is4510:
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jsr @RestoreGetCPUTemp
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lda #3 ; CPU_4510 constant
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ldx #0 ; load high byte of word
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rts
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@Is45GS02:
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jsr @RestoreGetCPUTemp
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lda #8 ; CPU_45GS02 constant
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ldx #0 ; load high byte of word
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rts
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@RestoreGetCPUTemp:
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; Save the 32-bit ZP pointer and data byte
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ldx #4
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@L11: lda @GetCPUTemp,x
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sta $fb,x
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dex
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bpl @L11
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rts
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; Temporary storage for the ZP locations we modify above
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@GetCPUTemp: .byte 0,0,0,0,0
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; 6502 type of cpu, check for a 2a03/2a07
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@IsNMOS:
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sed ; set decimal mode, no decimal mode on the 2a03/2a07
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lda #9
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clc
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adc #1 ; $01+$09 = $10 on 6502, $01+$09 = $0A on 2a03/2a07
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cld
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cmp #$0a
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beq @Is2a03
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lda #0 ; CPU_6502 constant
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beq @LoadXAndReturn
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@Is2a03:
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lda #7 ; CPU_2A0x constant
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bne @LoadXAndReturn
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; 65C02 cpu type, check for HuC6280
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@CheckHuC6280:
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ldx #6 ; CPU_HUC6280 constant
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.byte $22,$EA ; sax nop on HuC6280 (A=$06, X=$01), nop #$EA on 65C02 (A=$01, X=$06)
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bne @LoadXAndReturn
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; Check for 65816/65802
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@HasINCA:
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xba ; .byte $EB, put $01 in B accu (nop on 65C02/65SC02)
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dec a ; .byte $3A, A=$00
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xba ; .byte $EB, A=$01 if 65816/65802 and A=$00 if 65C02/65SC02
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inc a ; .byte $1A, A=$02 if 65816/65802 and A=$01 if 65C02/65SC02
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cmp #2
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beq @LoadXAndReturn
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; check for 65SC02
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ldy $F7
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ldx #0
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stx $F7
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.byte $F7,$F7 ; nop nop on 65SC02, smb7 $F7 on 65C02
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ldx $F7
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sty $F7
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cpx #$00
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bne @CheckHuC6280
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lda #4 ; CPU_65SC02 constant
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@LoadXAndReturn:
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ldx #0
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rts
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