mirror of https://github.com/cc65/cc65.git
751 lines
24 KiB
ArmAsm
751 lines
24 KiB
ArmAsm
;
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; Serial driver for the Apple IIgs Zilog Z8530.
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;
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; Colin Leroy-Mira <colin@colino.net>, 2023
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;
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; This software is licensed under the same license as cc65,
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; the zlib license (see LICENSE file).
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;
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; Documentation from http://www.applelogic.org/files/Z8530UM.pdf (pages
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; referred to where applicable)
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; and https://gswv.apple2.org.za/a2zine/Utils/Z8530_SCCsamples_info.txt
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.setcpu "65816"
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.include "zeropage.inc"
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.include "ser-kernel.inc"
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.include "ser-error.inc"
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.macpack module
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; ------------------------------------------------------------------------
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; Header. Includes jump table
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.ifdef __APPLE2ENH__
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module_header _a2e_gs_ser
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.else
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module_header _a2_gs_ser
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.endif
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; Driver signature
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.byte $73, $65, $72 ; "ser"
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.byte SER_API_VERSION ; Serial API version number
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; Library reference
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.addr $0000
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; Jump table
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.addr SER_INSTALL
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.addr SER_UNINSTALL
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.addr SER_OPEN
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.addr SER_CLOSE
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.addr SER_GET
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.addr SER_PUT
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.addr SER_STATUS
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.addr SER_IOCTL
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.addr SER_IRQ
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;----------------------------------------------------------------------------
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; Global variables
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.bss
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RecvHead: .res 1 ; Head of receive buffer
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RecvTail: .res 1 ; Tail of receive buffer
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RecvFreeCnt: .res 1 ; Number of bytes in receive buffer
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SendHead: .res 1 ; Head of send buffer
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SendTail: .res 1 ; Tail of send buffer
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SendFreeCnt: .res 1 ; Number of bytes in send buffer
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Stopped: .res 1 ; Flow-stopped flag
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RtsOff: .res 1
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HSType: .res 1 ; Flow-control type
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RecvBuf: .res 256 ; Receive buffers: 256 bytes
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SendBuf: .res 256 ; Send buffers: 256 bytes
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CurClockSource: .res 1 ; Whether to use BRG or RTxC for clock
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.data
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Opened: .byte $00 ; 1 when opened
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Channel: .byte $00 ; Channel B by default
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CurChanIrqFlags:.byte $00
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SerFlagOrig: .byte $00
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RxBitTable: .byte %00000000 ; SER_BITS_5, in WR_RX_CTRL (WR3)
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.byte %10000000 ; SER_BITS_6 (Ref page 5-7)
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.byte %01000000 ; SER_BITS_7
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.byte %11000000 ; SER_BITS_8
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TxBitTable: .byte %00000000 ; SER_BITS_5, in WR_TX_CTRL (WR5)
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.byte %01000000 ; SER_BITS_6 (Ref page 5-9)
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.byte %00100000 ; SER_BITS_7
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.byte %01100000 ; SER_BITS_8
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.rodata
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ClockMultiplier:.byte %01000000 ; Clock x16 (300-57600bps, WR4, ref page 5-8)
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.byte %10000000 ; Clock x32 (115200bps, ref page 5-8)
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ClockSource: .byte %01010000 ; Use baud rate generator (ch. B) (WR11, page 5-17)
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.byte %00000000 ; Use RTxC (115200bps) (ch. B)
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.byte %11010000 ; Use baud rate generator (ch. A)
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.byte %10000000 ; Use RTxC (115200bps) (ch. A)
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BrgEnabled: .byte %00000001 ; Baud rate generator on (WR14, page 5-19)
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.byte %00000000 ; BRG Off
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ChanIrqFlags: .byte %00000101 ; ANDed (RX/special IRQ, ch. B) (page 5-25)
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.byte %00101000 ; ANDed (RX/special IRQ, ch. A)
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ChanIrqMask: .byte %00000111 ; Ch. B IRQ flags mask
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.byte %00111000 ; Ch. A IRQ flags mask
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BaudTable: ; bit7 = 1 means setting is invalid
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; Indexes cc65 RS232 SER_BAUD enum
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; into WR12/13 register values
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; (Ref page 5-18 and 5-19)
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.word $FFFF ; SER_BAUD_45_5
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.word $FFFF ; SER_BAUD_50
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.word $FFFF ; SER_BAUD_75
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.word $FFFF ; SER_BAUD_110
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.word $FFFF ; SER_BAUD_134_5
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.word $FFFF ; SER_BAUD_150
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.word $017E ; SER_BAUD_300
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.word $FFFF ; SER_BAUD_600
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.word $005E ; SER_BAUD_1200
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.word $FFFF ; SER_BAUD_1800
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.word $002E ; SER_BAUD_2400
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.word $FFFF ; SER_BAUD_3600
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.word $0016 ; SER_BAUD_4800
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.word $FFFF ; SER_BAUD_7200
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.word $000A ; SER_BAUD_9600
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.word $0004 ; SER_BAUD_19200
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.word $0001 ; SER_BAUD_38400
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.word $0000 ; SER_BAUD_57600
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.word $0000 ; SER_BAUD_115200 (constant unused at that speed)
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.word $FFFF ; SER_BAUD_230400
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; About the speed selection: either we use the baud rate generator:
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; - Load the time constants from BaudTable into WR12/WR13
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; - Setup the TX/RX clock source to BRG (ClockSource into WR11)
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; - Setup the clock multiplier (WR4)
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; - Enable the baud rate generator (WR14)
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; In this case, the baud rate will be:
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; rate = crystal_clock/(2+BRG_time_constant))/(2*clock_multiplier)
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; Example: (3686400/(2+0x0004)) / (2*16) = 19200 bps
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;
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; Or we don't use the baud rate generator:
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; - Setup the TX/RX clock source to RTxC
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; - Setup the clock multiplier
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; - Disable the baud rate generator
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; - WR12 and 13 are ignored
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; In this case, the baud rate will be:
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; rate = crystal_clock/clock_multiplier
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; Example: 3686400/32 = 115200 bps
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StopTable: .byte %00000100 ; SER_STOP_1, in WR_TX_RX_CTRL (WR4)
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.byte %00001100 ; SER_STOP_2 (Ref page 5-8)
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ParityTable: .byte %00000000 ; SER_PAR_NONE, in WR_TX_RX_CTRL (WR4)
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.byte %00000001 ; SER_PAR_ODD (Ref page 5-8)
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.byte %00000011 ; SER_PAR_EVEN
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.byte $FF ; SER_PAR_MARK
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.byte $FF ; SER_PAR_SPACE
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; ------------------------------------------------------------------------
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; Addresses
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SCCAREG := $C039
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SCCBREG := $C038
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SCCADATA := $C03B
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SCCBDATA := $C03A
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; We're supposed to get SerFlag's address using GetAddr on ROMs 1 and 3.
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; (https://archive.org/details/IIgs_2523018_SCC_Access, page 9)
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; But, it's the same value as on ROM0. As we don't expect a ROM 4 anytime
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; soon with a different value, let's keep it simple.
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SER_FLAG := $E10104
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; ------------------------------------------------------------------------
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; Channels
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CHANNEL_B = 0
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CHANNEL_A = 1
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; ------------------------------------------------------------------------
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; Write registers, read registers, and values that interest us
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WR_INIT_CTRL = 0
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RR_INIT_STATUS = 0
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INIT_CTRL_CLEAR_EIRQ = %00010000
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INIT_CTRL_CLEAR_ERR = %00110000
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INIT_STATUS_READY = %00000100
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INIT_STATUS_RTS = %00100000
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WR_TX_RX_MODE_CTRL = 1
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TX_RX_MODE_OFF = %00000000
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TX_RX_MODE_RXIRQ = %00010001
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WR_RX_CTRL = 3 ; (Ref page 5-7)
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RR_RX_STATUS = 9 ; Corresponding status register
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RX_CTRL_ON = %00000001 ; ORed, Rx enabled
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RX_CTRL_OFF = %11111110 ; ANDed,Rx disabled
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WR_TX_RX_CTRL = 4
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RR_TX_RX_STATUS = 4
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WR_TX_CTRL = 5 ; (Ref page 5-9)
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RR_TX_STATUS = 5 ; Corresponding status register
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TX_CTRL_ON = %00001000 ; ORed, Tx enabled
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TX_CTRL_OFF = %11110111 ; ANDed,Tx disabled
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TX_DTR_ON = %01111111 ; ANDed,DTR ON (high)
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TX_DTR_OFF = %10000000 ; ORed, DTR OFF
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TX_RTS_ON = %00000010 ; ORed, RTS ON (low)
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TX_RTS_OFF = %11111101 ; ANDed, RTS OFF
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WR_MASTER_IRQ_RST = 9 ; (Ref page 5-14)
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MASTER_IRQ_SHUTDOWN = %00000010 ; STA'd
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MASTER_IRQ_MIE_RST = %00001010 ; STA'd
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MASTER_IRQ_SET = %00011001 ; STA'd
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WR_CLOCK_CTRL = 11 ; (Ref page 5-17)
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WR_BAUDL_CTRL = 12 ; (Ref page 5-18)
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WR_BAUDH_CTRL = 13 ; (Ref page 5-19)
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WR_MISC_CTRL = 14 ; (Ref page 5-19)
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WR_IRQ_CTRL = 15 ; (Ref page 5-20)
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IRQ_CLEANUP_EIRQ = %00001000
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RR_SPEC_COND_STATUS = 1 ; (Ref page 5-23)
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SPEC_COND_FRAMING_ERR = %01000000
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SPEC_COND_OVERRUN_ERR = %00100000
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RR_IRQ_STATUS = 2 ; (Ref page 5-24)
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IRQ_MASQ = %01110000 ; ANDed
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IRQ_RX = %00100000
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IRQ_SPECIAL = %01100000
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RR_INTR_PENDING_STATUS = 3 ; (Ref page 5-25)
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INTR_IS_RX = %00100100 ; ANDed (RX IRQ, channel A or B)
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.code
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; Read register value to A.
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; Input: X as channel
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; Y as register
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; Output: A
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readSSCReg:
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cpx #0
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bne ReadAreg
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sty SCCBREG
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lda SCCBREG
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rts
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ReadAreg:
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sty SCCAREG
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lda SCCAREG
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rts
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; Write value of A to a register.
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; Input: X as channel
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; Y as register
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writeSCCReg:
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cpx #0
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bne WriteAreg
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sty SCCBREG
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sta SCCBREG
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rts
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WriteAreg:
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sty SCCAREG
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sta SCCAREG
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rts
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;----------------------------------------------------------------------------
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; SER_INSTALL: Is called after the driver is loaded into memory. If possible,
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; check if the hardware is present. Must return an SER_ERR_xx code in a/x.
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;
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; Since we don't have to manage the IRQ vector on the Apple II, this is
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; actually the same as:
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;
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; SER_UNINSTALL: Is called before the driver is removed from memory.
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; No return code required (the driver is removed from memory on return).
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;
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; and:
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;
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; SER_CLOSE: Close the port and disable interrupts. Called without parameters.
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; Must return an SER_ERR_xx code in a/x.
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SER_INSTALL:
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SER_UNINSTALL:
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SER_CLOSE:
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; Check if this is a IIgs (Apple II Miscellaneous TechNote #7,
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; Apple II Family Identification)
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sec
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bit $C082
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jsr $FE1F
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bit $C080
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bcc IIgs
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lda #SER_ERR_NO_DEVICE ; Not a IIgs
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ldx #$00 ; Promote char return value
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rts
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IIgs:
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ldx Opened ; Check for open port
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beq :+
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ldx Channel
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; Deactivate interrupts
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sei
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ldy #WR_MASTER_IRQ_RST
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lda #MASTER_IRQ_SHUTDOWN
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jsr writeSCCReg
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ldy #WR_TX_RX_MODE_CTRL
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lda #TX_RX_MODE_OFF
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jsr writeSCCReg
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; Reset SerFlag to what it was
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lda SerFlagOrig
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sta SER_FLAG
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lda SCCBDATA
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; Clear external interrupts (twice)
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ldy #WR_INIT_CTRL
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lda #INIT_CTRL_CLEAR_EIRQ
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jsr writeSCCReg
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jsr writeSCCReg
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; Reset MIE for firmware use
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ldy #WR_MASTER_IRQ_RST
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lda #MASTER_IRQ_MIE_RST
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jsr writeSCCReg
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ldx #$00
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stx Opened ; Mark port as closed
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cli
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: txa ; Promote char return value
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rts
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getClockSource:
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.assert SER_PARAMS::BAUDRATE = 0, error
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lda (ptr1) ; Baudrate index - cc65 value
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cmp #SER_BAUD_115200
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lda #$00
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adc #$00
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sta CurClockSource ; 0 = BRG, 1 = RTxC
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rts
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;----------------------------------------------------------------------------
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; SER_OPEN: A pointer to a ser_params structure is passed in ptr1.
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; Must return an SER_ERR_xx code in a/x.
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SER_OPEN:
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sei
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; Check if the handshake setting is valid
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ldy #SER_PARAMS::HANDSHAKE ; Handshake
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lda (ptr1),y
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cmp #SER_HS_SW ; Not supported
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beq InvParam
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sta HSType ; Store flow control type
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; Initialize buffers
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ldy #$00
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sty Stopped
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sty RecvHead
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sty RecvTail
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sty SendHead
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sty SendTail
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dey ; Y = 255
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sty RecvFreeCnt
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sty SendFreeCnt
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ldx Channel
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ldy #RR_INIT_STATUS ; Hit rr0 once to sync up
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jsr readSSCReg
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ldy #WR_MISC_CTRL ; WR14: Turn everything off
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lda #$00
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jsr writeSCCReg
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jsr getClockSource ; Should we use BRG or RTxC?
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ldy #SER_PARAMS::STOPBITS ; WR4 setup: clock mult., stop & parity
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lda (ptr1),y ; Stop bits
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tay
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lda StopTable,y ; Get value
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pha
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ldy #SER_PARAMS::PARITY
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lda (ptr1),y ; Parity bits
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tay
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pla
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ora ParityTable,y ; Get value
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bmi InvParam
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ldy CurClockSource ; Clock multiplier
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ora ClockMultiplier,y
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ldy #WR_TX_RX_CTRL
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jsr writeSCCReg ; End of WR4 setup
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ldy CurClockSource ; WR11 setup: clock source
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cpx #CHANNEL_B
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beq SetClock
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iny ; Shift to get correct ClockSource val
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iny ; depending on our channel
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SetClock:
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lda ClockSource,y
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ldy #WR_CLOCK_CTRL
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jsr writeSCCReg ; End of WR11 setup
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lda ChanIrqFlags,x ; Store which IRQ bits we'll check
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sta CurChanIrqFlags
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SetBaud:
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.assert SER_PARAMS::BAUDRATE = 0, error
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lda (ptr1) ; Baudrate index - cc65 value
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asl
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tay
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lda BaudTable,y ; Get low byte of register value
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bpl BaudOK ; Verify baudrate is supported
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InvParam:
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lda #SER_ERR_INIT_FAILED
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ldy #$00 ; Mark port closed
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bra SetupOut
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BaudOK:
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phy ; WR12 setup: BRG time constant, low byte
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ldy #WR_BAUDL_CTRL ; Setting WR12 & 13 is useless if we're using
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jsr writeSCCReg ; RTxC, but doing it anyway makes code smaller
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ply
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iny
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lda BaudTable,y ; WR13 setup: BRG time constant, high byte
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ldy #WR_BAUDH_CTRL
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jsr writeSCCReg
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ldy CurClockSource ; WR14 setup: BRG enabling
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lda BrgEnabled,y
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ldy #WR_MISC_CTRL ; Time to turn this thing on
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jsr writeSCCReg
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ldy #SER_PARAMS::DATABITS ; WR3 setup: RX data bits
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lda (ptr1),y
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tay
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lda RxBitTable,y
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ora #RX_CTRL_ON ; and turn receiver on
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phy
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ldy #WR_RX_CTRL
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jsr writeSCCReg ; End of WR3 setup
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ply
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lda TxBitTable,y ; WR5 setup: TX data bits
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ora #TX_CTRL_ON ; and turn transmitter on
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and #TX_DTR_ON ; and turn DTR on
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sta RtsOff ; Save value for flow control
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ora #TX_RTS_ON ; and turn RTS on
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ldy #WR_TX_CTRL
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jsr writeSCCReg ; End of WR5 setup
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ldy #WR_IRQ_CTRL ; WR15 setup: IRQ
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lda #IRQ_CLEANUP_EIRQ
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jsr writeSCCReg
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ldy #WR_INIT_CTRL ; WR0 setup: clear existing IRQs
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lda #INIT_CTRL_CLEAR_EIRQ
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jsr writeSCCReg ; Clear (write twice)
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jsr writeSCCReg
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ldy #WR_TX_RX_MODE_CTRL ; WR1 setup: Activate RX IRQ
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lda #TX_RX_MODE_RXIRQ
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jsr writeSCCReg
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lda SCCBREG ; WR9 setup: Activate master IRQ
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ldy #WR_MASTER_IRQ_RST
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lda #MASTER_IRQ_SET
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jsr writeSCCReg
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lda SER_FLAG ; Get SerFlag's current value
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sta SerFlagOrig ; and save it
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ora ChanIrqMask,x ; Tell firmware which channel IRQs we want
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sta SER_FLAG
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ldy #$01 ; Mark port opened
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lda #SER_ERR_OK
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SetupOut:
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ldx #$00 ; Promote char return value
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sty Opened
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cli
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rts
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;----------------------------------------------------------------------------
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; SER_GET: Will fetch a character from the receive buffer and store it into the
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; variable pointed to by ptr1. If no data is available, SER_ERR_NO_DATA is
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; returned.
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SER_GET:
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ldx Channel
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lda RecvFreeCnt ; Check for buffer empty
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cmp #$FF
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beq NoData
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ldy Stopped ; Check for flow stopped
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beq :+
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cmp #63 ; Enough free?
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bcc :+
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stz Stopped ; Release flow control
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lda RtsOff
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ora #TX_RTS_ON
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ldy #WR_TX_CTRL
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jsr writeSCCReg
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: ldy RecvHead ; Get byte from buffer
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lda RecvBuf,y
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inc RecvHead
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inc RecvFreeCnt
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sta (ptr1)
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lda #SER_ERR_OK
|
|
.assert SER_ERR_OK = 0, error
|
|
tax
|
|
rts
|
|
NoData:
|
|
lda #SER_ERR_NO_DATA
|
|
ldx #$00 ; Promote char return value
|
|
rts
|
|
|
|
;----------------------------------------------------------------------------
|
|
; SER_PUT: Output character in A.
|
|
; Must return an SER_ERR_xx code in a/x.
|
|
|
|
SER_PUT:
|
|
ldx Channel
|
|
|
|
ldy SendFreeCnt ; Anything to send first?
|
|
iny ; Y = $FF?
|
|
beq :+
|
|
pha
|
|
lda #$00 ; TryHard = false
|
|
jsr TryToSend
|
|
pla
|
|
|
|
: ldy SendFreeCnt ; Do we have room to store byte?
|
|
bne :+
|
|
lda #SER_ERR_OVERFLOW
|
|
ldx #$00
|
|
rts
|
|
|
|
: ldy SendTail ; Put byte into send buffer & send
|
|
sta SendBuf,y
|
|
inc SendTail
|
|
dec SendFreeCnt
|
|
lda #$FF ; TryHard = true
|
|
jsr TryToSend
|
|
lda #SER_ERR_OK
|
|
.assert SER_ERR_OK = 0, error
|
|
tax
|
|
rts
|
|
|
|
;----------------------------------------------------------------------------
|
|
; SER_STATUS: Return the status in the variable pointed to by ptr1.
|
|
; Must return an SER_ERR_xx code in a/x.
|
|
; We provide the read register 0, containing interesting info like
|
|
; INIT_STATUS_READY (hardware handshake status) or INIT_STATUS_RTS
|
|
; (ready to send).
|
|
|
|
SER_STATUS:
|
|
ldx Channel
|
|
ldy #RR_INIT_STATUS
|
|
jsr readSSCReg
|
|
ldx #$00
|
|
sta (ptr1)
|
|
.assert SER_ERR_OK = 0, error
|
|
txa
|
|
rts
|
|
|
|
;----------------------------------------------------------------------------
|
|
; SER_IOCTL: Driver defined entry point. The wrapper will pass a pointer to ioctl
|
|
; specific data in ptr1, and the ioctl code in A.
|
|
; Sets communication channel A or B (A = 1, B = 0)
|
|
; Must return an SER_ERR_xx code in a/x.
|
|
|
|
SER_IOCTL:
|
|
ora ptr1+1 ; Check data msb and code to be 0
|
|
bne :+
|
|
|
|
ldx ptr1 ; Check data lsb to be 0 or 1
|
|
bmi :+
|
|
cpx #$02
|
|
bcs :+
|
|
|
|
stx Channel
|
|
.assert SER_ERR_OK = 0, error
|
|
tax
|
|
rts
|
|
|
|
: lda #SER_ERR_INV_IOCTL
|
|
ldx #$00 ; Promote char return value
|
|
rts
|
|
|
|
;----------------------------------------------------------------------------
|
|
; SER_IRQ: Called from the builtin runtime IRQ handler as a subroutine. All
|
|
; registers are already saved, no parameters are passed, but the carry flag
|
|
; is clear on entry. The routine must return with carry set if the interrupt
|
|
; was handled, otherwise with carry clear.
|
|
|
|
SER_IRQ:
|
|
ldy #RR_INTR_PENDING_STATUS ; IRQ status is always in A reg
|
|
sty SCCAREG
|
|
lda SCCAREG
|
|
|
|
and CurChanIrqFlags ; Is this ours?
|
|
beq Done
|
|
|
|
and #INTR_IS_RX ; Is this an RX irq?
|
|
beq CheckSpecial
|
|
|
|
ldx Channel
|
|
beq ReadBdata
|
|
lda SCCADATA
|
|
bra ReadDone
|
|
ReadBdata:
|
|
lda SCCBDATA ; Get byte
|
|
ReadDone:
|
|
ldx RecvFreeCnt ; Check if we have free space left
|
|
beq Flow ; Jump if no space in receive buffer
|
|
ldy RecvTail ; Load buffer pointer
|
|
sta RecvBuf,y ; Store received byte in buffer
|
|
inc RecvTail ; Increment buffer pointer
|
|
dec RecvFreeCnt ; Decrement free space counter
|
|
cpx #33
|
|
bcc Flow ; Assert flow control if buffer space low
|
|
rts ; Interrupt handled (carry already set)
|
|
|
|
CheckSpecial:
|
|
; Always check IRQ special flags from Channel B (Ref page 5-24)
|
|
ldy #RR_IRQ_STATUS
|
|
sty SCCBREG
|
|
lda SCCBREG
|
|
|
|
and #IRQ_MASQ
|
|
cmp #IRQ_SPECIAL
|
|
beq Special
|
|
|
|
; Clear exint
|
|
ldx Channel
|
|
ldy #WR_INIT_CTRL
|
|
lda #INIT_CTRL_CLEAR_EIRQ
|
|
jsr writeSCCReg
|
|
|
|
sec
|
|
rts
|
|
|
|
Flow: lda HSType ; Don't touch if no flow control
|
|
beq IRQDone
|
|
|
|
ldx Channel ; Assert flow control if buffer space too low
|
|
ldy #WR_TX_CTRL
|
|
lda RtsOff
|
|
jsr writeSCCReg
|
|
|
|
sta Stopped
|
|
IRQDone:sec ; Interrupt handled
|
|
Done: rts
|
|
|
|
Special:ldx Channel
|
|
ldy #RR_SPEC_COND_STATUS
|
|
jsr readSSCReg
|
|
|
|
tax
|
|
and #SPEC_COND_FRAMING_ERR
|
|
bne BadChar
|
|
txa
|
|
and #SPEC_COND_OVERRUN_ERR
|
|
beq BadChar
|
|
|
|
ldy #WR_INIT_CTRL
|
|
lda #INIT_CTRL_CLEAR_ERR
|
|
jsr writeSCCReg
|
|
|
|
sec
|
|
rts
|
|
|
|
BadChar:
|
|
cpx #CHANNEL_B
|
|
beq BadCharB
|
|
lda SCCADATA
|
|
bra BadCharDone
|
|
BadCharB:
|
|
lda SCCBDATA ; Remove char in error
|
|
BadCharDone:
|
|
sec
|
|
rts
|
|
|
|
;----------------------------------------------------------------------------
|
|
; Try to send a byte. Internal routine. A = TryHard, X = Channel
|
|
|
|
TryToSend:
|
|
sta tmp1 ; Remember tryHard flag
|
|
Again: lda SendFreeCnt ; Anything to send?
|
|
cmp #$FF
|
|
beq Quit ; No
|
|
|
|
lda Stopped ; Check for flow stopped
|
|
bne Quit ; Bail out if it is
|
|
|
|
Wait:
|
|
ldy #RR_INIT_STATUS
|
|
jsr readSSCReg ; Check that we're ready to send
|
|
tay
|
|
and #INIT_STATUS_READY
|
|
beq NotReady
|
|
|
|
tya
|
|
and #INIT_STATUS_RTS ; Ready to send
|
|
bne Send
|
|
|
|
NotReady:
|
|
bit tmp1 ; Keep trying if must try hard
|
|
bmi Wait
|
|
Quit: rts
|
|
|
|
Send: ldy SendHead ; Send byte
|
|
lda SendBuf,y
|
|
|
|
cpx #CHANNEL_B
|
|
beq WriteBdata
|
|
sta SCCADATA
|
|
bra WriteDone
|
|
WriteBdata:
|
|
sta SCCBDATA
|
|
WriteDone:
|
|
inc SendHead
|
|
inc SendFreeCnt
|
|
jmp Again ; Continue flushing TX buffer
|