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100 lines
3.9 KiB
PHP
100 lines
3.9 KiB
PHP
;
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; PET generic definitions.
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;
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; ---------------------------------------------------------------------------
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; Zero page, Commodore stuff
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VARTAB := $2A ; Pointer to start of BASIC variables
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MEMSIZE := $34 ; Size of memory installed
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TXTPTR := $77 ; Pointer into BASIC source code
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TIME := $8D ; 60HZ clock
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KEY_COUNT := $9E ; Number of keys in input buffer
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RVS := $9F ; Reverse flag
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CURS_FLAG := $A7 ; 1 = cursor off
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CURS_BLINK := $A8 ; Blink counter
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CURS_CHAR := $A9 ; Character under the cursor
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CURS_STATE := $AA ; Cursor blink state
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SCREEN_PTR := $C4 ; Pointer to current char in text screen
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CURS_X := $C6 ; Cursor column
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FNLEN := $D1 ; Length of filename
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LFN := $D2 ; Current Logical File Number
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SECADR := $D3 ; Secondary address
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DEVNUM := $D4 ; Device number
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SCR_LINELEN := $D5 ; Screen line length
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CURS_Y := $D8 ; Cursor row
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FNADR := $DA ; Pointer to file name
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; 80-Column CBMs
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KBDREPEAT80 := $E4
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KBDRPTRATE80 := $E5
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KBDRPTDELAY80 := $E6
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BASIC_BUF := $200 ; Location of command-line
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BASIC_BUF_LEN = 81 ; Maximum length of command-line
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KEY_BUF := $26F ; Keyboard buffer
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; 40-Column PETs/CBMs
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KBDRPTDELAY40 := $3E9
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KBDRPTRATE40 := $3EA
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KBDREPEAT40 := $3EE
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KBDREPEAT40B := $3F8
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;----------------------------------------------------------------------------
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; PET ROM type detection
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PET_DETECT := $FFFB
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PET_2000 = $CA
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PET_3000 = $FC
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PET_4000 = $FD
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;----------------------------------------------------------------------------
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; Vector and other locations
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IRQVec := $0090
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BRKVec := $0092
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NMIVec := $0094
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; ---------------------------------------------------------------------------
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; I/O: 6520 PIA1
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PIA1 := $E810 ; PIA1 base address
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PIA1_PORTA := PIA1+$0 ; Port A (PA) and data direction register A (DDRA)
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PIA1_PACTL := PIA1+$1 ; Port A control register (CRA)
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PIA1_PORTB := PIA1+$2 ; Port B (PB) and data direction register B (DDRB)
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PIA1_PBCTL := PIA1+$3 ; Port B control register (CRB)
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; ---------------------------------------------------------------------------
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; I/O: 6520 PIA2
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PIA2 := $E820 ; PIA2 base address
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PIA2_PORTA := PIA2+$0 ; Port A (PA) and data direction register A (DDRA)
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PIA2_PACTL := PIA2+$1 ; Port A control register (CRA)
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PIA2_PORTB := PIA2+$2 ; Port B (PB) and data direction register B (DDRB)
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PIA2_PBCTL := PIA2+$3 ; Port B control register (CRB)
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; ---------------------------------------------------------------------------
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; I/O: 6522 VIA
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VIA := $E840 ; VIA base address
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VIA_PB := VIA+$0 ; Port register B
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VIA_PA1 := VIA+$1 ; Port register A
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VIA_PRB := VIA+$0 ; *** Deprecated ***
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VIA_PRA := VIA+$1 ; *** Deprecated ***
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VIA_DDRB := VIA+$2 ; Data direction register B
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VIA_DDRA := VIA+$3 ; Data direction register A
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VIA_T1CL := VIA+$4 ; Timer 1, low byte
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VIA_T1CH := VIA+$5 ; Timer 1, high byte
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VIA_T1LL := VIA+$6 ; Timer 1 latch, low byte
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VIA_T1LH := VIA+$7 ; Timer 1 latch, high byte
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VIA_T2CL := VIA+$8 ; Timer 2, low byte
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VIA_T2CH := VIA+$9 ; Timer 2, high byte
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VIA_SR := VIA+$A ; Shift register
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VIA_CR := VIA+$B ; Auxiliary control register
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VIA_PCR := VIA+$C ; Peripheral control register
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VIA_IFR := VIA+$D ; Interrupt flag register
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VIA_IER := VIA+$E ; Interrupt enable register
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VIA_PA2 := VIA+$F ; Port register A w/o handshake
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