mirror of
https://github.com/cc65/cc65.git
synced 2024-07-03 06:29:36 +00:00
7e65f64c6a
and NMI to make sure the NMI handler is loaded into the low 16K of memory which are active when the control is passed from the ROM NMI stub to the user handler. git-svn-id: svn://svn.cc65.org/cc65/trunk@1086 b7a2c559-68d2-44c3-8de9-860c34a00d81
188 lines
4.0 KiB
PHP
188 lines
4.0 KiB
PHP
;
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; C64 generic definitions. Stolen from Elite128
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;
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; ---------------------------------------------------------------------------
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; Zero page, Commodore stuff
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ST = $90 ; IEC status byte
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FNAM_LEN = $B7 ; Length of filename
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SECADR = $B9 ; Secondary address
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DEVNUM = $BA ; Device number
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FNAM_BANK = $C7 ; Bank for filename
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FNAM_LO = $BB ; Address of filename
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FNAM_HI = $BC
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KEY_COUNT = $D0 ; Number of keys in input buffer
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MODE = $D7 ; 40/80 column mode flag
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CURS_X = $EC ; Cursor column
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CURS_Y = $EB ; Cursor row
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SCREEN_PTR = $E0 ; Pointer to current char in text screen
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CRAM_PTR = $E2 ; Pointer to current char in color RAM
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CHARCOLOR = $F1
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FKEY_COUNT = $D1 ; Characters for function key
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INIT_STATUS = $A04 ; Flag: Reset/NMI Status
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FKEY_LEN = $1000 ; Function key lengths
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FKEY_TEXT = $100A ; Function key texts
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; ---------------------------------------------------------------------------
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; Kernal routines
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; Direct entries
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CURS_ON = $CD6F
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CURS_OFF = $CD9F
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CLRSCR = $C142
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KBDREAD = $C006
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; ---------------------------------------------------------------------------
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; Vectors
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IRQVec = $0314
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BRKVec = $0316
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NMIVec = $0318
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KeyStoreVec = $033C
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; ---------------------------------------------------------------------------
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; I/O: VIC
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VIC = $D000
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VIC_SPR0_X = $D000
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VIC_SPR0_Y = $D001
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VIC_SPR1_X = $D002
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VIC_SPR1_Y = $D003
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VIC_SPR2_X = $D004
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VIC_SPR2_Y = $D005
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VIC_SPR3_X = $D006
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VIC_SPR3_Y = $D007
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VIC_SPR4_X = $D008
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VIC_SPR4_Y = $D009
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VIC_SPR5_X = $D00A
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VIC_SPR5_Y = $D00B
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VIC_SPR6_X = $D00C
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VIC_SPR6_Y = $D00D
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VIC_SPR7_X = $D00E
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VIC_SPR7_Y = $D00F
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VIC_SPR_HI_X = $D010
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VIC_SPR_ENA = $D015
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VIC_SPR_EXP_X = $D017
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VIC_SPR_EXP_Y = $D01D
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VIC_SPR_MCOLOR = $D01C
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VIC_SPR_BG_PRIO = $D01B
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VIC_SPR_MCOLOR0 = $D025
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VIC_SPR_MCOLOR1 = $D026
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VIC_SPR0_COLOR = $D027
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VIC_SPR1_COLOR = $D028
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VIC_SPR2_COLOR = $D029
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VIC_SPR3_COLOR = $D02A
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VIC_SPR4_COLOR = $D02B
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VIC_SPR5_COLOR = $D02C
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VIC_SPR6_COLOR = $D02D
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VIC_SPR7_COLOR = $D02E
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VIC_CTRL1 = $D011
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VIC_CTRL2 = $D016
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VIC_HLINE = $D012
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VIC_VIDEO_ADR = $D018
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VIC_IRR = $D019 ; Interrupt request register
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VIC_IMR = $D01A ; Interrupt mask register
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VIC_BORDERCOLOR = $D020
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VIC_BG_COLOR0 = $D021
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VIC_BG_COLOR1 = $D022
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VIC_BG_COLOR2 = $D023
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VIC_BG_COLOR3 = $D024
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; 128 stuff:
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VIC_KBD_128 = $D02F ; Extended kbd bits (visible in 64 mode)
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VIC_CLK_128 = $D030 ; Clock rate register (visible in 64 mode)
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; ---------------------------------------------------------------------------
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; I/O: SID
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SID = $D400
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SID_S1Lo = $D400
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SID_S1Hi = $D401
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SID_PB1Lo = $D402
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SID_PB1Hi = $D403
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SID_Ctl1 = $D404
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SID_AD1 = $D405
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SID_SUR1 = $D406
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SID_S2Lo = $D407
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SID_S2Hi = $D408
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SID_PB2Lo = $D409
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SID_PB2Hi = $D40A
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SID_Ctl2 = $D40B
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SID_AD2 = $D40C
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SID_SUR2 = $D40D
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SID_S3Lo = $D40E
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SID_S3Hi = $D40F
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SID_PB3Lo = $D410
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SID_PB3Hi = $D411
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SID_Ctl3 = $D412
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SID_AD3 = $D413
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SID_SUR3 = $D414
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SID_FltLo = $D415
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SID_FltHi = $D416
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SID_FltCtl = $D417
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SID_Amp = $D418
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SID_ADConv1 = $D419
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SID_ADConv2 = $D41A
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SID_Noise = $D41B
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SID_Read3 = $D41C
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; ---------------------------------------------------------------------------
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; I/O: VDC (128 only)
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VDC_INDEX = $D600
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VDC_DATA = $D601
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; ---------------------------------------------------------------------------
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; I/O: CIAs
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CIA1 = $DC00
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CIA1_PRA = $DC00
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CIA1_PRB = $DC01
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CIA1_DDRA = $DC02
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CIA1_DDRB = $DC03
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CIA1_ICR = $DC0D
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CIA1_CRA = $DC0E
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CIA1_CRB = $DC0F
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CIA2 = $DD00
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CIA2_PRA = $DD00
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CIA2_PRB = $DD01
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CIA2_DDRA = $DD02
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CIA2_DDRB = $DD03
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CIA2_ICR = $DD0D
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CIA2_CRA = $DD0E
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CIA2_CRB = $DD0F
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; ---------------------------------------------------------------------------
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; I/O: MMU
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MMU_CR = $FF00
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CC65_MMU_CFG = $0E ; Bank 0 with kernal ROM
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; ---------------------------------------------------------------------------
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; Super CPU
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SCPU_VIC_Bank1 = $D075
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SCPU_Slow = $D07A
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SCPU_Fast = $D07B
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SCPU_EnableRegs = $D07E
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SCPU_DisableRegs= $D07F
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SCPU_Detect = $D0BC
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