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https://github.com/cc65/cc65.git
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266 lines
9.0 KiB
C
266 lines
9.0 KiB
C
/*****************************************************************************/
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/* */
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/* _mikey.h */
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/* */
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/* Atari Lynx, Mikey chip register hardware structures */
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/* */
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/* */
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/* This software is provided 'as-is', without any expressed or implied */
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/* warranty. In no event will the authors be held liable for any damages */
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/* arising from the use of this software. */
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/* */
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/* Permission is granted to anyone to use this software for any purpose, */
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/* including commercial applications, and to alter it and redistribute it */
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/* freely, subject to the following restrictions: */
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/* */
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/* 1. The origin of this software must not be misrepresented; you must not */
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/* claim that you wrote the original software. If you use this software */
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/* in a product, an acknowledgment in the product documentation would be */
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/* appreciated but is not required. */
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/* 2. Altered source versions must be plainly marked as such, and must not */
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/* be misrepresented as being the original software. */
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/* 3. This notice may not be removed or altered from any source */
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/* distribution. */
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/* */
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/*****************************************************************************/
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#ifndef __MIKEY_H
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#define __MIKEY_H
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/* Timer structure */
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typedef struct _mikey_timer {
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unsigned char reload;
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unsigned char control;
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unsigned char count;
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unsigned char control2;
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} _mikey_timer;
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typedef struct _mikey_all_timers {
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struct _mikey_timer timer[8];
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} _mikey_all_timers;
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/* Audio channel structure */
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typedef struct _mikey_audio {
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unsigned char volume;
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unsigned char feedback;
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unsigned char dac;
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unsigned char shiftlo;
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unsigned char reload;
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unsigned char control;
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unsigned char count;
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unsigned char other;
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} _mikey_audio;
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/* Define a structure with the mikey register offsets */
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struct __mikey {
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struct _mikey_timer timer0; // 0xFD00
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struct _mikey_timer timer1; // 0xFD04
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struct _mikey_timer timer2; // 0xFD08
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struct _mikey_timer timer3; // 0xFD0C
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struct _mikey_timer timer4; // 0xFD10
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struct _mikey_timer timer5; // 0xFD14
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struct _mikey_timer timer6; // 0xFD18
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struct _mikey_timer timer7; // 0xFD1C
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struct _mikey_audio channel_a; // 0xFD20
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struct _mikey_audio channel_b; // 0xFD28
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struct _mikey_audio channel_c; // 0xFD30
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struct _mikey_audio channel_d; // 0xFD38
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unsigned char attena; // 0xFD40 ?? not yet allocated?
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unsigned char attenb; // 0xFD41 |
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unsigned char attenc; // 0xFD42 |
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unsigned char attend; // 0xFD43 |
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unsigned char panning; // 0xFD44 |
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unsigned char unused0[11]; // 0xFD45 - 0xFD4F not used
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unsigned char mstereo; // 0xFD50 stereo control bits
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unsigned char unused1[47]; // 0xFD51 - 0xFD7F not used
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unsigned char intrst; // 0xFD80 interrupt poll 0
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unsigned char intset; // 0xFD81 interrupt poll 1
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unsigned char unused2[2]; // 0xFD82 - 0xFD83 not used
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unsigned char magrdy0; // 0xFD84 mag tape channel0 ready bit
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unsigned char magrdy1; // 0xFD85 mag tape channel1 ready bit
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unsigned char audin; // 0xFD86 audio in
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unsigned char sysctl1; // 0xFD87 control bits
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unsigned char mikeyrev; // 0xFD88 mikey hardware rev
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unsigned char mikeysrev; // 0xFD89 mikey software rev
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unsigned char iodir; // 0xFD8A parallel i/o data dir
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unsigned char iodat; // 0xFD8B parallel data
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unsigned char serctl; // 0xFD8C serial control register
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unsigned char serdat; // 0xFD8D serial data
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unsigned char unused3[2]; // 0xFD8E - 0xFD8F not used
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unsigned char sdoneack; // 0xFD90 suzy done acknowledge
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unsigned char cpusleep; // 0xFD91 cpu bus request disable
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unsigned char dispctl; // 0xFD92 video bus request enable, viddma
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unsigned char pkbkup; // 0xFD93 magic 'P' count
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unsigned char *scrbase; // 0xFD94 start address of video display
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unsigned char unused4[6]; // 0xFD96 - 0xFD9B not used
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unsigned char mtest0; // 0xFD9C
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unsigned char mtest1; // 0xFD9D
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unsigned char mtest2; // 0xFD9E
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unsigned char unused5; // 0xFD9F not used
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unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes
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unsigned char unused6[64]; // 0xFDC0 - 0xFDFF not used
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unsigned char bootrom[504]; // 0xFE00 - 0xFFD8 boot rom
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unsigned char reserved; // 0xFFD8 reserved for future hardware
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unsigned char mapctl; // 0xFFF9 map control register
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struct {
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unsigned char *nmi; // 0xFFFA NMI vector
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unsigned char *reset; // 0xFFFB reset vector
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unsigned char *irq; // 0xFFFC IRQ vector
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} vectors;
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};
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// TIM_CONTROLA control bit definitions
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enum {
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ENABLE_INT = 0x80,
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RESET_DONE = 0x40,
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ENABLE_RELOAD = 0x10,
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ENABLE_COUNT = 0x08
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};
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// AUD_CONTROL control bit definitions
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enum {
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FEEDBACK_7 = 0x80,
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ENABLE_INTEGRATE = 0x20
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};
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// Audio and timer clock settings for source period
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enum {
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AUD_LINKING = 0x07,
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AUD_64 = 0x06,
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AUD_32 = 0x05,
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AUD_16 = 0x04,
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AUD_8 = 0x03,
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AUD_4 = 0x02,
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AUD_2 = 0x01,
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AUD_1 = 0x00
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};
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// TIM_CONTROLB control bit definitions
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enum {
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TIMER_DONE = 0x08,
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LAST_CLOCK = 0x04,
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BORROW_IN = 0x02,
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BORROW_OUT = 0x01
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};
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// MPAN and MSTEREO registers bit definitions
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enum {
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LEFT3_SELECT = 0x80,
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LEFT2_SELECT = 0x40,
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LEFT1_SELECT = 0x20,
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LEFT0_SELECT = 0x10,
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RIGHT3_SELECT = 0x08,
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RIGHT2_SELECT = 0x04,
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RIGHT1_SELECT = 0x02,
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RIGHT0_SELECT = 0x01,
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LEFT_ATTENMASK = 0xF0,
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RIGHT_ATTENMASK = 0x0F
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};
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// Interrupt Reset and Set bit definitions
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enum {
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TIMER7_INT = 0x80,
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TIMER6_INT = 0x40,
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TIMER5_INT = 0x20,
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TIMER4_INT = 0x10,
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TIMER3_INT = 0x08,
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TIMER2_INT = 0x04,
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TIMER1_INT = 0x02,
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TIMER0_INT = 0x01,
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SERIAL_INT = TIMER4_INT,
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VERTICAL_INT = TIMER2_INT,
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HORIZONTAL_INT = TIMER0_INT
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};
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// SYSCTL1 bit definitions
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enum {
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POWERON = 0x02,
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CART_ADDR_STROBE = 0x01
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};
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// IODIR and IODAT bit definitions
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enum {
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AUDIN_BIT = 0x10, // different from AUDIN address
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READ_ENABLE = 0x10, // same bit for AUDIN_BIT
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RESTLESS = 0x08,
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NOEXP = 0x04, // if set, redeye is not connected
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CART_ADDR_DATA = 0x02, //
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CART_POWER_OFF = 0x02, // same bit for CART_ADDR_DATA
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EXTERNAL_POWER = 0x01
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};
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// SERCTL bit definitions for write operations
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enum {
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TXINTEN = 0x80,
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RXINTEN = 0x40,
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PAREN = 0x10,
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RESETERR = 0x08,
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TXOPEN = 0x04,
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TXBRK = 0x02,
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PAREVEN = 0x01
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};
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// SERCTL bit definitions for read operations
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enum {
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TXRDY = 0x80,
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RXRDY = 0x40,
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TXEMPTY = 0x20,
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PARERR = 0x10,
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OVERRUN = 0x08,
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FRAMERR = 0x04,
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RXBRK = 0x02,
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PARBIT = 0x01
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};
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// DISPCTL bit definitions
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enum {
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DISP_COLOR = 0x08, // must be set to 1
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DISP_FOURBIT = 0x04, // must be set to 1
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DISP_FLIP = 0x02, //
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DMA_ENABLE = 0x01 // must be set to 1
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};
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// MTEST0 bit definitions
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enum {
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AT_CNT16 = 0x80,
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AT_TEST = 0x40,
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XCLKEN = 0x20,
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UART_TURBO = 0x10,
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ROM_SEL = 0x08,
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ROM_TEST = 0x04,
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M_TEST = 0x02,
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CPU_TEST = 0x01
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};
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// MTEST1 bit definitions
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enum {
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P_CNT16 = 0x40,
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REF_CNT16 = 0x20,
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VID_TRIG = 0x10,
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REF_TRIG = 0x08,
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VID_DMA_DIS = 0x04,
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REF_FAST = 0x02,
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REF_DIS = 0x01
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};
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// MTEST2 bit definitions
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enum {
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V_STROBE = 0x10,
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V_ZERO = 0x08,
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H_120 = 0x04,
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H_ZERO = 0x02,
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V_BLANKEF = 0x01
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};
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// MAPCTL bit definitions
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enum {
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TURBO_DISABLE = 0x80,
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VECTOR_SPACE = 0x08,
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ROM_SPACE = 0x04,
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MIKEY_SPACE = 0x02,
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SUZY_SPACE = 0x01
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};
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#endif
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