Renamed emulator
This commit is contained in:
PeronTheDuck
parent
e66085eb25
commit
00f7cf1726
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@ -0,0 +1,32 @@
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# ___0 _0__
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A 0__0 1010
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--------abs---------
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abs ___0 11__
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absX ___1 11__
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absY ___1 1___
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--------------------
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rel 0000 ___1
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--------ind---------
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ind ___a bb0c
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a b c
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ind 0 1 0
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X 0 0 1
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Y 1 0 1
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_: opcode?
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ind 0110 1100
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Xind ___0 0001
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indY ___1 0001
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--------------------
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zpg ___0 01__
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zpgX ___1 01__
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zpgY 10_1 0110
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___a bb_c
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c => uses X|Y
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a => x / y
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@ -0,0 +1,24 @@
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pub fn get_size(addr_mode: AddressingMode) -> usize {
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OP_SIZES[addr_mode as usize]
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}
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//A,abs,absX,absY,imm,impl,ind,indX,indY,rel,zpg,zpgX,zpgY
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//1, 3, 3, 3, 2, 1, 3, 2, 2, 2, 2, 2, 2
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pub static OP_SIZES: [usize; 13] = [1, 3, 3, 3, 2, 1, 3, 2, 2, 2, 2, 2, 2];
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#[derive(Debug, Copy, Clone, PartialEq)]
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pub enum AddressingMode {
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A = 0, // LSR A
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ABS, // LDA $1234
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ABSX, // STA $3000,X
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ABSY, // AND $4000,Y
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IMM, // LDA #$10
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IMPL, // CLC
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IND, // JMP ($FFFC)
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INDX, // LDA ($40,X)
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INDY, // LDA ($40),Y
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REL, // LABEL // +4
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ZPG, // LDA $10
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ZPGX, // LDA $10,X
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ZPGY, // LDA $10,Y
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}
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@ -0,0 +1,68 @@
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#[repr(u8)]
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#[derive(PartialEq, Copy, Clone, Debug)]
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pub enum Flags {
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Negative = 128,
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Overflow = 64,
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AlwaysOne = 32,
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Break = 16,
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Decimal = 8,
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Int = 4,
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Zero = 2,
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Carry = 1,
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}
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#[allow(non_snake_case)]
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pub struct Cpu {
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pub A: u8,
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pub X: u8,
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pub Y: u8,
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pub PC: u16,
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pub flags: u8,
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}
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impl Cpu {
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pub fn test(&self, flag: Flags) -> bool {
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(self.flags & flag as u8) != 0
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}
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pub fn set_flag(&mut self, flag: Flags, status: bool) {
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if status {
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self.flags |= flag as u8;
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} else {
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self.flags &= 0xFF - flag as u8;
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}
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}
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pub fn add_a(&mut self, n: u8) {
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let n = n as u16;
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let a = self.A as u16;
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let res = n + a;
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if res > 0xFF {
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self.set_flag(Flags::Carry, true);
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} else {
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self.set_flag(Flags::Carry, false);
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}
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self.set_a((res & 0xFF) as u8);
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}
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pub fn set_a(&mut self, value: u8) {
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self.set_flag(Flags::Zero, value == 0x00); // Set Zero if A is zero
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self.set_flag(Flags::Negative, value & 0x80 != 0); // Test sign bit
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self.A = value;
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}
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}
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impl std::default::Default for Cpu {
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fn default() -> Self {
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Self {
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A: 0x00,
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X: 0x00,
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Y: 0x00,
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PC: 0x0000,
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flags: 0b_0010_0000,
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}
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}
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}
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impl std::fmt::Debug for Cpu {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> Result<(), std::fmt::Error> {
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write!(
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f,
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"Registers: \n PC: {:04X}\n A: {:02X} X: {:02X} Y: {:02X}\nNV-BDIZC\n{:08b}",
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self.PC, self.A, self.X, self.Y, self.flags
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)
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}
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}
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@ -0,0 +1,194 @@
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use super::cpu::{Cpu, Flags};
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use super::error;
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use super::opcodes;
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use super::OpcodeType;
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use super::{addressing_modes::get_size, AddressingMode};
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fn invalid_mode<T>(mode_used: AddressingMode) -> T {
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panic!("The addressign mode used ({:?}) is either not valid for this opcode, or expects an argument which was not provided",mode_used)
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}
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static RESET_VEC_ADDR: usize = 0xFFFC;
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macro_rules! fetch {
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($self:ident PC+$off:expr) => {
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$self.ram[$self.cpu.PC as usize + $off]
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};
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($self:ident $addr:expr) => {
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$self.ram[$addr as usize]
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};
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($self:ident D $addr:expr) => {
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($self.ram[$addr as usize + 1] as u16) << 8 | $self.ram[$addr as usize] as u16
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};
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}
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macro_rules! operation {
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($self:ident A+$b:expr) => {
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$self.cpu.A.wrapping_add($b as u8)
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};
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($self:ident X+$b:expr) => {
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$self.cpu.X.wrapping_add($b as u8)
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};
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(unwrap $arg:ident $addr:ident) => {
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$arg.unwrap_or_else(|| invalid_mode($addr.addr_mode))
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};
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}
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pub struct Emulator {
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pub cycles: usize,
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pub ram: [u8; 0x10000],
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pub cpu: Cpu,
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}
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impl Emulator {
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pub fn new() -> Self {
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Self {
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cycles: 0,
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ram: [0x00; 0x10000],
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cpu: Cpu::default(),
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}
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}
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pub fn init(&mut self) -> Result<(), error::EmulatorError> {
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let lo: u16 = self.ram[RESET_VEC_ADDR] as u16;
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let hi: u16 = self.ram[RESET_VEC_ADDR + 1] as u16;
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let addr = hi << 8 | lo;
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self.cpu.PC = addr;
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Ok(())
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}
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pub fn step(&mut self) -> Result<(), error::EmulatorError> {
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if self.cycles == 0 {
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println!("Initializing");
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self.init()?;
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}
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if self.cpu.test(Flags::Break) {
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return Err(error::EmulatorError::Break);
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}
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println!("Step on {:04X}", self.cpu.PC);
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let code = self.ram[self.cpu.PC as usize];
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let code = match opcodes::from_code(code) {
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None => return Err(error::EmulatorError::UnknownOp(code)),
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Some(v) => v,
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};
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println!(" Opcode {:?}", code.name);
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let arg: Option<u16> = match code.addr_mode {
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AddressingMode::IMPL => None, // No argument
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AddressingMode::A => None, // No argument
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AddressingMode::IMM => {
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// Next byte is the argument
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let addr = fetch!(self PC+1);
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Some(addr as u16)
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}
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AddressingMode::ABS => {
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// Next 2 bytes are an address from where to fetch the real argument
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let addr = self.cpu.PC as usize + 1;
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Some(fetch!(self D addr) as u16)
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}
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AddressingMode::ZPG => {
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// Next byte is an address from the range 0x0000-0x00FF
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let addr = self.cpu.PC as usize + 1;
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Some(fetch!(self addr) as u16)
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}
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AddressingMode::INDX => {
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// Take the next byte and add it to X,
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// then use the result as an address and fetch 2 bytes
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let arg = fetch!(self PC+1); // Opcode arg
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let addr: u8 = operation!(self X+arg); // Zero-page addr
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let addr_lo = self.ram[addr as usize] as usize;
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let addr_hi = self.ram[addr.wrapping_add(1) as usize] as usize;
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let res_addr = addr_hi << 8 | addr_lo;
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Some(res_addr as u16)
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}
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AddressingMode::REL => {
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// Add PC with the next byte
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let arg = fetch!(self PC+1) as u8 as i8 as isize;
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let pc = self.cpu.PC as usize as isize;
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let new_pc = (arg + pc) & 0xFFFF;
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Some(new_pc as u16)
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}
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_ => {
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unimplemented!("Unimplemented addressing mode {:?}", code.addr_mode);
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}
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};
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let mut branch_taken = false; // Don't update PC if we take a branch
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println!(" Argument: {:#04X?}", arg);
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match code.name {
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OpcodeType::BRK => {
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println!("Stepped on break. Ending");
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println!("{:#?}", self.cpu);
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return Err(error::EmulatorError::Break);
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}
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OpcodeType::NOP => {}
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OpcodeType::LDA => match code.addr_mode {
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AddressingMode::IMM => self.cpu.set_a(operation!(unwrap arg code) as u8),
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AddressingMode::ABS => self.cpu.set_a(fetch!(self operation!(unwrap arg code))),
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AddressingMode::ZPG => self.cpu.set_a(fetch!(self operation!(unwrap arg code))),
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_ => panic!("Invalid addressing mode for {:?}", code.name),
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},
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OpcodeType::STA => match code.addr_mode {
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AddressingMode::ABS => self.ram[operation!(unwrap arg code) as usize] = self.cpu.A,
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AddressingMode::ZPG => self.ram[operation!(unwrap arg code) as usize] = self.cpu.A,
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AddressingMode::INDX => self.ram[operation!(unwrap arg code) as usize] = self.cpu.A,
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_ => panic!("Invalid addressing mode for {:?}", code.name),
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},
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OpcodeType::ADC => match code.addr_mode {
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AddressingMode::IMM => self.cpu.add_a(operation!(unwrap arg code) as u8),
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_ => panic!("Invalid addressing mode for {:?}", code.name),
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},
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OpcodeType::JMP => match code.addr_mode {
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AddressingMode::ABS => self.cpu.PC = operation!(unwrap arg code) as u16,
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_ => panic!("Invalid addressing mode for {:?}", code.name),
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},
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OpcodeType::BEQ if code.addr_mode == AddressingMode::REL => {
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if self.cpu.test(Flags::Zero) {
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self.cpu.PC = operation!(unwrap arg code);
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branch_taken = true;
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}
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}
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OpcodeType::BNE if code.addr_mode == AddressingMode::REL => {
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if !self.cpu.test(Flags::Zero) {
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self.cpu.PC = operation!(unwrap arg code);
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branch_taken = true;
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}
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}
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_ => {
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unimplemented!(
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"Unimplemented opcode {:?} with {:?}",
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code.name,
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code.addr_mode
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);
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}
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}
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if branch_taken || code.name == OpcodeType::JMP {
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println!("Don't increment PC");
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} else {
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self.cpu.PC += get_size(code.addr_mode) as u16;
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}
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self.cycles += 1;
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Ok(())
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}
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pub fn restart(&mut self) {
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self.cycles = 0;
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self.ram = [0x00; 0x10000];
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self.cpu = Cpu::default();
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}
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}
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mod test {
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#[test]
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fn test_flags() {
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use super::{Cpu, Flags};
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let mut cpu: Cpu = Cpu::default();
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cpu.set_flag(Flags::Zero, true);
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assert_eq!(cpu.test(Flags::Zero), true);
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cpu.set_flag(Flags::Zero, false);
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assert_eq!(cpu.test(Flags::Zero), false);
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cpu.set_flag(Flags::Zero, true);
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cpu.set_flag(Flags::Negative, true);
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cpu.set_flag(Flags::Int, true);
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assert_eq!(cpu.test(Flags::Zero), true);
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assert_eq!(cpu.test(Flags::Negative), true);
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assert_eq!(cpu.test(Flags::Int), true);
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cpu.set_flag(Flags::Negative, false);
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assert_eq!(cpu.test(Flags::Zero), true);
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assert_eq!(cpu.test(Flags::Negative), false);
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assert_eq!(cpu.test(Flags::Int), true);
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}
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}
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@ -0,0 +1,25 @@
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use std::boxed::Box;
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use std::error::Error;
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use std::fmt::{Display, Error as FmtError, Formatter};
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#[derive(Debug)]
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pub enum EmulatorError {
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UnknownOp(u8),
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Break,
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Suberror(Box<dyn Error>),
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}
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impl Display for EmulatorError {
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fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), FmtError> {
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write!(
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f,
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"Emulator Error: {}",
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match self {
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EmulatorError::Suberror(e) => e.description().to_string(),
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EmulatorError::Break => "Emulator Terminated".to_string(),
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EmulatorError::UnknownOp(code) => format!("Unknown OP with code {:02X}", code),
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}
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)
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}
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}
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impl Error for EmulatorError {}
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@ -0,0 +1,9 @@
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pub mod error;
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mod addressing_modes;
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use addressing_modes::AddressingMode;
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mod opcodes;
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use opcodes::OpcodeType;
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mod cpu;
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mod emulator;
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pub use emulator::Emulator;
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@ -0,0 +1,883 @@
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use super::addressing_modes::AddressingMode;
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pub const OPCODES: [Option<OpcodeData>; 0x100] = [
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Some(OpcodeData {
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name: OpcodeType::BRK,
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addr_mode: AddressingMode::IMPL,
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}),
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::INDX,
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}),
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None,
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None,
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None,
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::ZPG,
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}),
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Some(OpcodeData {
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name: OpcodeType::ASL,
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addr_mode: AddressingMode::ZPG,
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}),
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None,
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Some(OpcodeData {
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name: OpcodeType::PHP,
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addr_mode: AddressingMode::IMPL,
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}),
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::IMM,
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}),
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Some(OpcodeData {
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name: OpcodeType::ASL,
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addr_mode: AddressingMode::A,
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}),
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None,
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None,
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::ABS,
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}),
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Some(OpcodeData {
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name: OpcodeType::ASL,
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addr_mode: AddressingMode::ABS,
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}),
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None,
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Some(OpcodeData {
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name: OpcodeType::BPL,
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addr_mode: AddressingMode::REL,
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}),
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::INDY,
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}),
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None,
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None,
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None,
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::ZPGX,
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}),
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Some(OpcodeData {
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name: OpcodeType::ASL,
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addr_mode: AddressingMode::ZPGX,
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}),
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None,
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Some(OpcodeData {
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name: OpcodeType::CLC,
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addr_mode: AddressingMode::IMPL,
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}),
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::ABSY,
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}),
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None,
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None,
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None,
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Some(OpcodeData {
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name: OpcodeType::ORA,
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addr_mode: AddressingMode::ABSX,
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}),
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Some(OpcodeData {
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name: OpcodeType::ASL,
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addr_mode: AddressingMode::ABSX,
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}),
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None,
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Some(OpcodeData {
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name: OpcodeType::JSR,
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addr_mode: AddressingMode::ABS,
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}),
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Some(OpcodeData {
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name: OpcodeType::AND,
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addr_mode: AddressingMode::INDX,
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}),
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None,
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None,
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Some(OpcodeData {
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name: OpcodeType::BIT,
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addr_mode: AddressingMode::ZPG,
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}),
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Some(OpcodeData {
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name: OpcodeType::AND,
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addr_mode: AddressingMode::ZPG,
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}),
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Some(OpcodeData {
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name: OpcodeType::ROL,
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addr_mode: AddressingMode::ZPG,
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}),
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None,
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Some(OpcodeData {
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name: OpcodeType::PLP,
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addr_mode: AddressingMode::IMPL,
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}),
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Some(OpcodeData {
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name: OpcodeType::AND,
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addr_mode: AddressingMode::IMM,
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}),
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Some(OpcodeData {
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name: OpcodeType::ROL,
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addr_mode: AddressingMode::A,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BIT,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::AND,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROL,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BMI,
|
||||
addr_mode: AddressingMode::REL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::AND,
|
||||
addr_mode: AddressingMode::INDY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::AND,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROL,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SEC,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::AND,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::AND,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROL,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::RTI,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::INDX,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LSR,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::PHA,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LSR,
|
||||
addr_mode: AddressingMode::A,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::JMP,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LSR,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BVC,
|
||||
addr_mode: AddressingMode::REL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::INDY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LSR,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CLI,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::EOR,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LSR,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::RTS,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::INDX,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROR,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::PLA,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROR,
|
||||
addr_mode: AddressingMode::A,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::JMP,
|
||||
addr_mode: AddressingMode::IND,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROR,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BVS,
|
||||
addr_mode: AddressingMode::REL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::INDY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROR,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SEI,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ADC,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::ROR,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STA,
|
||||
addr_mode: AddressingMode::INDX,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STY,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STA,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STX,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::DEY,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::TXA,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STY,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STA,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STX,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BCC,
|
||||
addr_mode: AddressingMode::REL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STA,
|
||||
addr_mode: AddressingMode::INDY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STY,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STA,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STX,
|
||||
addr_mode: AddressingMode::ZPGY,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::TYA,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STA,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::TXS,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::STA,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDY,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::INDX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDX,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDY,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDX,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::TAY,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::TAX,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDY,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDX,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BCS,
|
||||
addr_mode: AddressingMode::REL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::INDY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDY,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDX,
|
||||
addr_mode: AddressingMode::ZPGY,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CLV,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::TSX,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDY,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDA,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::LDX,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CPY,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::INDX,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CPY,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::DEC,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::INY,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::DEX,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CPY,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::DEC,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BNE,
|
||||
addr_mode: AddressingMode::REL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::INDY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::DEC,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CLD,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CMP,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::DEC,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CPX,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::INDX,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CPX,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::INC,
|
||||
addr_mode: AddressingMode::ZPG,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::INX,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::IMM,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::NOP,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::CPX,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::INC,
|
||||
addr_mode: AddressingMode::ABS,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::BEQ,
|
||||
addr_mode: AddressingMode::REL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::INDY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::INC,
|
||||
addr_mode: AddressingMode::ZPGX,
|
||||
}),
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SED,
|
||||
addr_mode: AddressingMode::IMPL,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::ABSY,
|
||||
}),
|
||||
None,
|
||||
None,
|
||||
None,
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::SBC,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
Some(OpcodeData {
|
||||
name: OpcodeType::INC,
|
||||
addr_mode: AddressingMode::ABSX,
|
||||
}),
|
||||
None,
|
||||
];
|
||||
/* pub fn get_code(name: OpcodeType, addr_mode: AddressingMode) -> Result<u8, Error> {
|
||||
for (i, opcode) in OPCODES.iter().enumerate() {
|
||||
match opcode {
|
||||
None => continue,
|
||||
Some(ref opcode) => {
|
||||
if opcode.name == name && opcode.addr_mode == addr_mode {
|
||||
return Ok((i & 0xFF) as u8);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Err(Error::UnkownOpcode { name: name.into() })
|
||||
} */
|
||||
|
||||
#[derive(Debug, PartialEq, Copy, Clone)]
|
||||
pub enum OpcodeType {
|
||||
ADC,
|
||||
AND,
|
||||
ASL,
|
||||
BCC, // Branch ops
|
||||
BCS, // Branch ops
|
||||
BEQ, // Branch ops
|
||||
BIT,
|
||||
BMI, // Branch ops
|
||||
BNE, // Branch ops
|
||||
BPL, // Branch ops
|
||||
BRK,
|
||||
BVC, // Branch ops
|
||||
BVS, // Branch ops
|
||||
CLC,
|
||||
CLD,
|
||||
CLI,
|
||||
CLV,
|
||||
CMP,
|
||||
CPX,
|
||||
CPY,
|
||||
DEC,
|
||||
DEX,
|
||||
DEY,
|
||||
EOR,
|
||||
INC,
|
||||
INX,
|
||||
INY,
|
||||
JMP,
|
||||
JSR,
|
||||
LDA,
|
||||
LDX,
|
||||
LDY,
|
||||
LSR,
|
||||
NOP,
|
||||
ORA,
|
||||
PHA,
|
||||
PHP,
|
||||
PLA,
|
||||
PLP,
|
||||
ROL,
|
||||
ROR,
|
||||
RTI,
|
||||
RTS,
|
||||
SBC,
|
||||
SEC,
|
||||
SED,
|
||||
SEI,
|
||||
STA,
|
||||
STX,
|
||||
STY,
|
||||
TAX,
|
||||
TAY,
|
||||
TSX,
|
||||
TXA,
|
||||
TXS,
|
||||
TYA,
|
||||
}
|
||||
impl OpcodeType {
|
||||
pub fn identify<'s, S: std::ops::Deref<Target = &'s str>>(
|
||||
string: &S,
|
||||
) -> Result<OpcodeType, ()> {
|
||||
match **string {
|
||||
"ADC" => Ok(OpcodeType::ADC),
|
||||
"AND" => Ok(OpcodeType::AND),
|
||||
"ASL" => Ok(OpcodeType::ASL),
|
||||
"BCC" => Ok(OpcodeType::BCC),
|
||||
"BCS" => Ok(OpcodeType::BCS),
|
||||
"BEQ" => Ok(OpcodeType::BEQ),
|
||||
"BIT" => Ok(OpcodeType::BIT),
|
||||
"BMI" => Ok(OpcodeType::BMI),
|
||||
"BNE" => Ok(OpcodeType::BNE),
|
||||
"BPL" => Ok(OpcodeType::BPL),
|
||||
"BRK" => Ok(OpcodeType::BRK),
|
||||
"BVC" => Ok(OpcodeType::BVC),
|
||||
"BVS" => Ok(OpcodeType::BVS),
|
||||
"CLC" => Ok(OpcodeType::CLC),
|
||||
"CLD" => Ok(OpcodeType::CLD),
|
||||
"CLI" => Ok(OpcodeType::CLI),
|
||||
"CLV" => Ok(OpcodeType::CLV),
|
||||
"CMP" => Ok(OpcodeType::CMP),
|
||||
"CPX" => Ok(OpcodeType::CPX),
|
||||
"CPY" => Ok(OpcodeType::CPY),
|
||||
"DEC" => Ok(OpcodeType::DEC),
|
||||
"DEX" => Ok(OpcodeType::DEX),
|
||||
"DEY" => Ok(OpcodeType::DEY),
|
||||
"EOR" => Ok(OpcodeType::EOR),
|
||||
"INC" => Ok(OpcodeType::INC),
|
||||
"INX" => Ok(OpcodeType::INX),
|
||||
"INY" => Ok(OpcodeType::INY),
|
||||
"JMP" => Ok(OpcodeType::JMP),
|
||||
"JSR" => Ok(OpcodeType::JSR),
|
||||
"LDA" => Ok(OpcodeType::LDA),
|
||||
"LDX" => Ok(OpcodeType::LDX),
|
||||
"LDY" => Ok(OpcodeType::LDY),
|
||||
"LSR" => Ok(OpcodeType::LSR),
|
||||
"NOP" => Ok(OpcodeType::NOP),
|
||||
"ORA" => Ok(OpcodeType::ORA),
|
||||
"PHA" => Ok(OpcodeType::PHA),
|
||||
"PHP" => Ok(OpcodeType::PHP),
|
||||
"PLA" => Ok(OpcodeType::PLA),
|
||||
"PLP" => Ok(OpcodeType::PLP),
|
||||
"ROL" => Ok(OpcodeType::ROL),
|
||||
"ROR" => Ok(OpcodeType::ROR),
|
||||
"RTI" => Ok(OpcodeType::RTI),
|
||||
"RTS" => Ok(OpcodeType::RTS),
|
||||
"SBC" => Ok(OpcodeType::SBC),
|
||||
"SEC" => Ok(OpcodeType::SEC),
|
||||
"SED" => Ok(OpcodeType::SED),
|
||||
"SEI" => Ok(OpcodeType::SEI),
|
||||
"STA" => Ok(OpcodeType::STA),
|
||||
"STX" => Ok(OpcodeType::STX),
|
||||
"STY" => Ok(OpcodeType::STY),
|
||||
"TAX" => Ok(OpcodeType::TAX),
|
||||
"TAY" => Ok(OpcodeType::TAY),
|
||||
"TSX" => Ok(OpcodeType::TSX),
|
||||
"TXA" => Ok(OpcodeType::TXA),
|
||||
"TXS" => Ok(OpcodeType::TXS),
|
||||
"TYA" => Ok(OpcodeType::TYA),
|
||||
_ => Err(()),
|
||||
}
|
||||
}
|
||||
pub fn is_branch_op(self) -> bool {
|
||||
use OpcodeType::*;
|
||||
let branch_ops = [BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS];
|
||||
branch_ops.contains(&self)
|
||||
}
|
||||
}
|
||||
impl std::convert::Into<String> for OpcodeType {
|
||||
fn into(self) -> String {
|
||||
format!("{:?}", self)
|
||||
}
|
||||
}
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
pub struct OpcodeData {
|
||||
pub name: OpcodeType,
|
||||
pub addr_mode: AddressingMode,
|
||||
}
|
||||
|
||||
pub fn from_code(code: u8) -> Option<OpcodeData> {
|
||||
OPCODES[code as usize]
|
||||
}
|
||||
|
||||
mod test {
|
||||
#[test]
|
||||
fn test_opcode_name() {
|
||||
use super::OpcodeType;
|
||||
let strings = vec![("LDA", true), ("STA", true), ("JMP", true), ("xd", false)];
|
||||
for (string, is_ok) in strings.iter() {
|
||||
let res = OpcodeType::identify(&string);
|
||||
println!("{} -> {:?}", string, res);
|
||||
assert_eq!(res.is_ok(), *is_ok);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
ADC 011A AA01
|
||||
AND 001A AA01
|
||||
ASL 000A AA10
|
||||
BCC 1001 0000
|
||||
BCS 1011 0000
|
||||
BEQ 1111 0000
|
||||
BIT 0010 A100
|
||||
BMI 0011 0000
|
||||
BNE 1101 0000
|
||||
BPL 0001 0000
|
||||
BRK 0000 0000
|
||||
BVC 0101 0000
|
||||
BVS 0111 0000
|
||||
CLC 0001 1000
|
||||
CLD 1101 1000
|
||||
CLI 0101 1000
|
||||
CLV 1011 1000
|
||||
CMP 110A AA01
|
||||
CPA 1110 AA00
|
||||
CPY 1100 AA00
|
||||
DEC 110A A110
|
||||
DEA 1100 1010
|
||||
DEY 1000 1000
|
||||
EOR 010A AA01
|
||||
INC 111A A110
|
||||
INA 1110 1000
|
||||
INY 1100 1000
|
||||
JMP 01A0 1100
|
||||
JSR 0010 0000
|
||||
LDA 10AA AA01
|
||||
LDA 101A AA10
|
||||
LDY 101A AA00
|
||||
LSR 010A AA10
|
||||
NOP 1110 1010
|
||||
ORA 000A AA01
|
||||
PHA 0100 1000
|
||||
PHP 0000 1000
|
||||
PLA 0110 1000
|
||||
PLP 0010 1000
|
||||
ROL 001A AA10
|
||||
ROR 011A AA10
|
||||
RTI 0100 0000
|
||||
RTS 0110 0000
|
||||
SBC 111A AA01
|
||||
SEC 0011 1000
|
||||
SED 1111 1000
|
||||
SEI 0111 0000
|
||||
STA 100A AA01
|
||||
STA 100A A110
|
||||
STY 100A A100
|
||||
TAA 1010 1010
|
||||
TAY 1010 1000
|
||||
TSA 1011 1010
|
||||
TAA 1000 1010
|
||||
TAS 1001 1010
|
||||
TYA 1001 1000
|
||||
Loading…
Reference in New Issue