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opcode and disassembler generatory (python)
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jborza
parent
6cd265c578
commit
0d63342137
176
data/6502_ops.csv
Normal file
176
data/6502_ops.csv
Normal file
@ -0,0 +1,176 @@
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opcode,mnemonic,addressing mode,bytes,cycles,flags
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0x69,ADC,IMM,2,2,CZidbVN
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0x65,ADC,ZP,2,3,CZidbVN
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0x75,ADC,ZPX,2,4,CZidbVN
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0x6d,ADC,ABS,3,4,CZidbVN
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0x7d,ADC,ABSX,3,4,CZidbVN
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0x79,ADC,ABSY,3,4,CZidbVN
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0x61,ADC,INDX,2,6,CZidbVN
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0x71,ADC,INDY,2,5,CZidbVN
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0x29,AND,IMM,2,2,cZidbvN
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0x25,AND,ZP,2,3,cZidbvN
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0x35,AND,ZPX,2,4,cZidbvN
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0x2d,AND,ABS,3,4,cZidbvN
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0x3d,AND,ABSX,3,4,cZidbvN
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0x39,AND,ABSY,3,4,cZidbvN
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0x21,AND,INDX,2,6,cZidbvN
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0x31,AND,INDY,2,5,cZidbvN
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0x0a,ASL,ACC,1,2,CZidbvN
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0x06,ASL,ZP,2,5,CZidbvN
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0x16,ASL,ZPX,2,6,CZidbvN
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0x0e,ASL,ABS,3,6,CZidbvN
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0x1e,ASL,ABSX,3,7,CZidbvN
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0x90,BCC,REL,2,2/3,czidbvn
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0xB0,BCS,REL,2,2/3,czidbvn
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0xF0,BEQ,REL,2,2/3,czidbvn
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0x30,BMI,REL,2,2/3,czidbvn
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0xD0,BNE,REL,2,2/3,czidbvn
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0x10,BPL,REL,2,2/3,czidbvn
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0x50,BVC,REL,2,2/3,czidbvn
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0x70,BVS,REL,2,2/3,czidbvn
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0x24,BIT,ZP,2,3,cZidbVN
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0x2c,BIT,ABS,3,4,cZidbVN
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0x00,BRK,IMP,1,7,czidbvn
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0x18,CLC,IMP,1,2,Czidbvn
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0xd8,CLD,IMP,1,2,cziDbvn
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0x58,CLI,IMP,1,2,czIdbvn
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0xb8,CLV,IMP,1,2,czidbVn
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0xea,NOP,IMP,1,2,czidbvn
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0x48,PHA,IMP,1,3,czidbvn
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0x68,PLA,IMP,1,4,cZidbvN
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0x08,PHP,IMP,1,3,czidbvn
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0x28,PLP,IMP,1,4,CZIDBVN
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0x40,RTI,IMP,1,6,czidbvn
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0x60,RTS,IMP,1,6,czidbvn
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0x38,SEC,IMP,1,2,Czidbvn
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0xf8,SED,IMP,1,2,cziDbvn
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0x78,SEI,IMP,1,2,czIdbvn
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0xaa,TAX,IMP,1,2,cZidbvN
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0x8a,TXA,IMP,1,2,cZidbvN
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0xa8,TAY,IMP,1,2,cZidbvN
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0x98,TYA,IMP,1,2,cZidbvN
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0xba,TSX,IMP,1,2,cZidbvN
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0x9a,TXS,IMP,1,2,czidbvn
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0xc9,CMP,IMM,2,2,CZidbvN
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0xc5,CMP,ZP,2,3,CZidbvN
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0xd5,CMP,ZPX,2,4,CZidbvN
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0xcd,CMP,ABS,3,4,CZidbvN
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0xdd,CMP,ABSX,3,4,CZidbvN
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0xd9,CMP,ABSY,3,4,CZidbvN
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0xc1,CMP,INDX,2,6,CZidbvN
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0xd1,CMP,INDY,2,5,CZidbvN
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0xe0,CPX,IMM,2,2,CZidbvN
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0xe4,CPX,ZP,2,3,CZidbvN
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0xec,CPX,ABS,3,4,CZidbvN
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0xc0,CPY,IMM,2,2,CZidbvN
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0xc4,CPY,ZP,2,3,CZidbvN
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0xcc,CPY,ABS,3,4,CZidbvN
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0xc6,DEC,ZP,2,5,cZidbvN
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0xd6,DEC,ZPX,2,6,cZidbvN
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0xce,DEC,ABS,3,6,cZidbvN
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0xde,DEC,ABSX,3,7,cZidbvN
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0xca,DEX,IMP,1,2,cZidbvN
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0x88,DEY,IMP,1,2,cZidbvN
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0xe8,INX,IMP,1,2,cZidbvN
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0xc8,INY,IMP,1,2,cZidbvN
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0x49,EOR,IMM,2,2,cZidbvN
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0x45,EOR,ZP,2,3,cZidbvN
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0x55,EOR,ZPX,2,4,cZidbvN
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0x4d,EOR,ABS,3,4,cZidbvN
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0x5d,EOR,ABSX,3,4,cZidbvN
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0x59,EOR,ABSY,3,4,cZidbvN
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0x41,EOR,INDX,2,6,cZidbvN
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0x51,EOR,INDY,2,5,cZidbvN
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0xe6,INC,ZP,2,5,cZidbvN
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0xf6,INC,ZPX,2,6,cZidbvN
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0xee,INC,ABS,3,6,cZidbvN
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0xfe,INC,ABSX,3,7,cZidbvN
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0x4c,JMP,ABS,3,3,czidbvn
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0x6c,JMP,IND,3,5,czidbvn
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0x20,JSR,ABS,3,6,czidbvn
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0xa9,LDA,IMM,2,2,cZidbvN
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0xa5,LDA,ZP,2,3,cZidbvN
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0xb5,LDA,ZPX,2,4,cZidbvN
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0xad,LDA,ABS,3,4,cZidbvN
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0xbd,LDA,ABSX,3,4,cZidbvN
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0xb9,LDA,ABSY,3,4,cZidbvN
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0xa1,LDA,INDX,2,6,cZidbvN
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0xb1,LDA,INDY,2,5,cZidbvN
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0xa2,LDX,IMM,2,2,cZidbvN
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0xa6,LDX,ZP,2,3,cZidbvN
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0xb6,LDX,ZPY,2,4,cZidbvN
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0xae,LDX,ABS,3,4,cZidbvN
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0xbe,LDX,ABSY,3,4,cZidbvN
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0xa0,LDY,IMM,2,2,cZidbvN
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0xa4,LDY,ZP,2,3,cZidbvN
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0xb4,LDY,ZPX,2,4,cZidbvN
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0xac,LDY,ABS,3,4,cZidbvN
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0xbc,LDY,ABSX,3,4,cZidbvN
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0x4a,LSR,ACC,1,2,CZidbvN
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0x46,LSR,ZP,2,5,CZidbvN
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0x56,LSR,ZPX,2,6,CZidbvN
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0x4e,LSR,ABS,3,6,CZidbvN
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0x5e,LSR,ABSX,3,7,CZidbvN
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0x09,ORA,IMM,2,2,cZidbvN
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0x05,ORA,ZP,2,3,cZidbvN
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0x15,ORA,ZPX,2,4,cZidbvN
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0x0d,ORA,ABS,3,4,cZidbvN
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0x1d,ORA,ABSX,3,4,cZidbvN
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0x19,ORA,ABSY,3,4,cZidbvN
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0x01,ORA,INDX,2,6,cZidbvN
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0x11,ORA,INDY,2,5,cZidbvN
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0x2a,ROL,ACC,1,2,CZidbvN
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0x26,ROL,ZP,2,5,CZidbvN
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0x36,ROL,ZPX,2,6,CZidbvN
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0x2e,ROL,ABS,3,6,CZidbvN
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0x3e,ROL,ABSX,3,7,CZidbvN
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0x6a,ROR,ACC,1,2,CZidbvN
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0x66,ROR,ZP,2,5,CZidbvN
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0x76,ROR,ZPX,2,6,CZidbvN
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0x7e,ROR,ABS,3,6,CZidbvN
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0x6e,ROR,ABSX,3,7,CZidbvN
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0xe9,SBC,IMM,2,2,CZidbVN
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0xe5,SBC,ZP,2,3,CZidbVN
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0xf5,SBC,ZPX,2,4,CZidbVN
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0xed,SBC,ABS,3,4,CZidbVN
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0xfd,SBC,ABSX,3,4,CZidbVN
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0xf9,SBC,ABSY,3,4,CZidbVN
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0xe1,SBC,INDX,2,6,CZidbVN
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0xf1,SBC,INDY,2,5,CZidbVN
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0x85,STA,ZP,2,3,czidbvn
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0x95,STA,ZPX,2,4,czidbvn
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0x8d,STA,ABS,3,4,czidbvn
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0x9d,STA,ABSX,3,5,czidbvn
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0x99,STA,ABSY,3,5,czidbvn
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0x81,STA,INDX,2,6,czidbvn
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0x91,STA,INDY,2,6,czidbvn
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0x86,STX,ZP,2,3,czidbvn
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0x96,STX,ZPY,2,4,czidbvn
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0x8e,STX,ABS,3,4,czidbvn
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0x84,STY,ZP,2,3,czidbvn
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0x94,STY,ZPX,2,4,czidbvn
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0x8c,STY,ABS,3,4,czidbvn
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61
data/generate_disassembler.py
Normal file
61
data/generate_disassembler.py
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@ -0,0 +1,61 @@
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import csv
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with open('disassembler.c','w') as outfile:
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with open('6502_ops.csv','r') as file:
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reader = csv.DictReader(file)
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for op in reader:
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print(op)
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args = int(op['bytes'])
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addr_mode = op['addressing mode']
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suffix = '_'+ addr_mode if addr_mode != 'IMP' else ''
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mnemonic = op['mnemonic']
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name = mnemonic + suffix
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outfile.write('case %s: ' % name)
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outfile.write('sprintf(op, ')
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if(addr_mode == 'IMP'):
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outfile.write('"%s"' % mnemonic)
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else: #all other addressing modes use name + suffix
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outfile.write('"%s ' % mnemonic)
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if(addr_mode == 'IMM'):
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outfile.write('#$%02X')
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elif(addr_mode == 'ACC'):
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outfile.write("A")
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elif(addr_mode.startswith('ZP')):
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outfile.write("$%02X")
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if(addr_mode == 'ZPX'):
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outfile.write(",X")
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if(addr_mode == 'ZPY'):
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outfile.write(",Y")
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elif(addr_mode.startswith('ABS')):
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outfile.write("$%02X%02X")
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if(addr_mode == 'ABSX'):
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outfile.write(",X")
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if(addr_mode == 'ABSY'):
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outfile.write(",Y")
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elif(addr_mode == 'IND'):
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outfile.write("($%02X%02X)")
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elif(addr_mode == 'INDX'):
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outfile.write("($%02X,X)")
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elif(addr_mode == 'INDY'):
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outfile.write("($%02X),Y")
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elif(addr_mode == 'REL'):
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outfile.write("$%02X")
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#end format string
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outfile.write("\"")
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#append bytes, reversed as of little endian
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if(args > 2):
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outfile.write(", code[2]")
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if(args > 1):
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outfile.write(", code[1]")
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outfile.write(');')
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if(args > 1):
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outfile.write("bytes = %s;" % args)
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#sprintf(op, "%s"' % ())
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#outfile.write('#define %s %s' % (name, op['opcode']))
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outfile.write('break;')
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outfile.write('\n')
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13
data/generate_opcodes.py
Normal file
13
data/generate_opcodes.py
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@ -0,0 +1,13 @@
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import csv
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with open('opcodes.h','w') as outfile:
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with open('6502_ops.csv','r') as file:
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reader = csv.DictReader(file)
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for op in reader:
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print(op)
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addr_mode = op['addressing mode']
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suffix = '_'+ addr_mode if addr_mode != 'IMP' else ''
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name = op['mnemonic'] + suffix
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outfile.write('#define %s %s' % (name, op['opcode']))
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outfile.write('\n')
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