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https://github.com/jborza/emu6502.git
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added stubs for missing instructions to cpu
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jborza
parent
6dfa71c5dc
commit
555568c10b
245
cpu.c
245
cpu.c
@ -65,63 +65,100 @@ word read_word(State6502 * state, word address) {
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int emulate_6502_op(State6502 * state) {
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byte* opcode = &state->memory[state->pc++];
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switch (*opcode) {
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case ADC_IMM: unimplemented_instruction(state); break;
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case ADC_ZP: unimplemented_instruction(state); break;
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case ADC_ZPX: unimplemented_instruction(state); break;
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case ADC_ABS: unimplemented_instruction(state); break;
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case ADC_ABSX: unimplemented_instruction(state); break;
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case ADC_ABSY: unimplemented_instruction(state); break;
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case ADC_INDX: unimplemented_instruction(state); break;
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case ADC_INDY: unimplemented_instruction(state); break;
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case AND_IMM: unimplemented_instruction(state); break;
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case AND_ZP: unimplemented_instruction(state); break;
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case AND_ZPX: unimplemented_instruction(state); break;
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case AND_ABS: unimplemented_instruction(state); break;
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case AND_ABSX: unimplemented_instruction(state); break;
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case AND_ABSY: unimplemented_instruction(state); break;
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case AND_INDX: unimplemented_instruction(state); break;
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case AND_INDY: unimplemented_instruction(state); break;
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case ASL_ACC: unimplemented_instruction(state); break;
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case ASL_ZP: unimplemented_instruction(state); break;
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case ASL_ZPX: unimplemented_instruction(state); break;
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case ASL_ABS: unimplemented_instruction(state); break;
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case ASL_ABSX: unimplemented_instruction(state); break;
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case BCC_REL: unimplemented_instruction(state); break;
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case BCS_REL: unimplemented_instruction(state); break;
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case BEQ_REL: unimplemented_instruction(state); break;
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case BMI_REL: unimplemented_instruction(state); break;
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case BNE_REL: unimplemented_instruction(state); break;
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case BPL_REL: unimplemented_instruction(state); break;
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case BVC_REL: unimplemented_instruction(state); break;
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case BVS_REL: unimplemented_instruction(state); break;
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case BIT_ZP: unimplemented_instruction(state); break;
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case BIT_ABS: unimplemented_instruction(state); break;
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case BRK: state->running = 0;
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state->flags.b = 1;
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break; //BRK
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case CLC: unimplemented_instruction(state); break;
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case CLD: unimplemented_instruction(state); break;
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case CLI: unimplemented_instruction(state); break;
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case CLV: unimplemented_instruction(state); break;
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case NOP: break; //NOP
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case ORA_INDX: //ORA, indirect, x
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{
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//pre-indexed indirect
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//zero-page address is added to x register
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byte indirect_address = pop_byte(state) + state->x;
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//pointing to address of a word holding the address of the operand
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word address = read_word(state, indirect_address);
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ZP: //ORA, zero page
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{
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byte address = pop_byte(state);
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_INDY: //ORA, indirect, y (post_indexed)
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{
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//post-indexed indirect
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//zero-page address as an argument
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byte indirect_address = pop_byte(state);
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//the address and the following byte is read as a word, adding Y register
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word address = read_word(state, indirect_address) + state->y;
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_IMM:
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ORA(state, pop_byte(state));
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break;
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case ORA_ZPX:
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{
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byte address = pop_byte(state) + state->x;
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ABS:
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{
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word address = pop_word(state);
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ABSX:
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{
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word address = pop_word(state) + state->x;
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ABSY:
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{
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word address = pop_word(state) + state->y;
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ORA(state, state->memory[address]);
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break;
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}
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case PHA: unimplemented_instruction(state); break;
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case PLA: unimplemented_instruction(state); break;
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case PHP: unimplemented_instruction(state); break;
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case PLP: unimplemented_instruction(state); break;
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case RTI: unimplemented_instruction(state); break;
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case RTS: unimplemented_instruction(state); break;
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case SEC: unimplemented_instruction(state); break;
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case SED: unimplemented_instruction(state); break;
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case SEI: unimplemented_instruction(state); break;
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case TAX: unimplemented_instruction(state); break;
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case TXA: unimplemented_instruction(state); break;
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case TAY: unimplemented_instruction(state); break;
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case TYA: unimplemented_instruction(state); break;
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case TSX: unimplemented_instruction(state); break;
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case TXS: unimplemented_instruction(state); break;
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case CMP_IMM: unimplemented_instruction(state); break;
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case CMP_ZP: unimplemented_instruction(state); break;
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case CMP_ZPX: unimplemented_instruction(state); break;
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case CMP_ABS: unimplemented_instruction(state); break;
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case CMP_ABSX: unimplemented_instruction(state); break;
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case CMP_ABSY: unimplemented_instruction(state); break;
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case CMP_INDX: unimplemented_instruction(state); break;
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case CMP_INDY: unimplemented_instruction(state); break;
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case CPX_IMM: unimplemented_instruction(state); break;
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case CPX_ZP: unimplemented_instruction(state); break;
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case CPX_ABS: unimplemented_instruction(state); break;
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case CPY_IMM: unimplemented_instruction(state); break;
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case CPY_ZP: unimplemented_instruction(state); break;
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case CPY_ABS: unimplemented_instruction(state); break;
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case DEC_ZP: unimplemented_instruction(state); break;
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case DEC_ZPX: unimplemented_instruction(state); break;
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case DEC_ABS: unimplemented_instruction(state); break;
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case DEC_ABSX: unimplemented_instruction(state); break;
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case DEX: unimplemented_instruction(state); break;
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case DEY: unimplemented_instruction(state); break;
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case INX: unimplemented_instruction(state); break;
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case INY: unimplemented_instruction(state); break;
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case EOR_IMM: unimplemented_instruction(state); break;
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case EOR_ZP: unimplemented_instruction(state); break;
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case EOR_ZPX: unimplemented_instruction(state); break;
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case EOR_ABS: unimplemented_instruction(state); break;
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case EOR_ABSX: unimplemented_instruction(state); break;
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case EOR_ABSY: unimplemented_instruction(state); break;
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case EOR_INDX: unimplemented_instruction(state); break;
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case EOR_INDY: unimplemented_instruction(state); break;
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case INC_ZP: unimplemented_instruction(state); break;
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case INC_ZPX: unimplemented_instruction(state); break;
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case INC_ABS: unimplemented_instruction(state); break;
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case INC_ABSX: unimplemented_instruction(state); break;
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case JMP_ABS: unimplemented_instruction(state); break;
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case JMP_IND: unimplemented_instruction(state); break;
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case JSR_ABS: unimplemented_instruction(state); break;
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case LDA_IMM:
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{
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LDA(state, pop_byte(state));
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@ -166,7 +203,7 @@ int emulate_6502_op(State6502 * state) {
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word address = read_word(state, indirect_address);
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LDA(state, state->memory[address]);
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break;
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}
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}
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case LDA_INDY:
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{
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//post-indexed indirect
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@ -177,6 +214,106 @@ int emulate_6502_op(State6502 * state) {
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LDA(state, state->memory[address]);
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break;
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}
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case LDX_IMM: unimplemented_instruction(state); break;
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case LDX_ZP: unimplemented_instruction(state); break;
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case LDX_ZPY: unimplemented_instruction(state); break;
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case LDX_ABS: unimplemented_instruction(state); break;
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case LDX_ABSY: unimplemented_instruction(state); break;
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case LDY_IMM: unimplemented_instruction(state); break;
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case LDY_ZP: unimplemented_instruction(state); break;
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case LDY_ZPX: unimplemented_instruction(state); break;
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case LDY_ABS: unimplemented_instruction(state); break;
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case LDY_ABSX: unimplemented_instruction(state); break;
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case LSR_ACC: unimplemented_instruction(state); break;
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case LSR_ZP: unimplemented_instruction(state); break;
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case LSR_ZPX: unimplemented_instruction(state); break;
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case LSR_ABS: unimplemented_instruction(state); break;
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case LSR_ABSX: unimplemented_instruction(state); break;
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case ORA_IMM:
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ORA(state, pop_byte(state));
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break;
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case ORA_ZP: //ORA, zero page
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{
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byte address = pop_byte(state);
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ZPX:
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{
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byte address = pop_byte(state) + state->x;
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ABS:
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{
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word address = pop_word(state);
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ABSX:
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{
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word address = pop_word(state) + state->x;
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_ABSY:
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{
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word address = pop_word(state) + state->y;
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_INDX: //ORA, indirect, x
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{
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//pre-indexed indirect
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//zero-page address is added to x register
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byte indirect_address = pop_byte(state) + state->x;
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//pointing to address of a word holding the address of the operand
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word address = read_word(state, indirect_address);
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ORA(state, state->memory[address]);
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break;
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}
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case ORA_INDY: //ORA, indirect, y (post_indexed)
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{
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//post-indexed indirect
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//zero-page address as an argument
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byte indirect_address = pop_byte(state);
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//the address and the following byte is read as a word, adding Y register
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word address = read_word(state, indirect_address) + state->y;
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ORA(state, state->memory[address]);
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break;
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}
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case ROL_ACC: unimplemented_instruction(state); break;
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case ROL_ZP: unimplemented_instruction(state); break;
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case ROL_ZPX: unimplemented_instruction(state); break;
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case ROL_ABS: unimplemented_instruction(state); break;
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case ROL_ABSX: unimplemented_instruction(state); break;
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case ROR_ACC: unimplemented_instruction(state); break;
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case ROR_ZP: unimplemented_instruction(state); break;
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case ROR_ZPX: unimplemented_instruction(state); break;
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case ROR_ABS: unimplemented_instruction(state); break;
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case ROR_ABSX: unimplemented_instruction(state); break;
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case SBC_IMM: unimplemented_instruction(state); break;
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case SBC_ZP: unimplemented_instruction(state); break;
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case SBC_ZPX: unimplemented_instruction(state); break;
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case SBC_ABS: unimplemented_instruction(state); break;
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case SBC_ABSX: unimplemented_instruction(state); break;
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case SBC_ABSY: unimplemented_instruction(state); break;
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case SBC_INDX: unimplemented_instruction(state); break;
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case SBC_INDY: unimplemented_instruction(state); break;
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case STA_ZP: unimplemented_instruction(state); break;
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case STA_ZPX: unimplemented_instruction(state); break;
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case STA_ABS: unimplemented_instruction(state); break;
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case STA_ABSX: unimplemented_instruction(state); break;
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case STA_ABSY: unimplemented_instruction(state); break;
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case STA_INDX: unimplemented_instruction(state); break;
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case STA_INDY: unimplemented_instruction(state); break;
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case STX_ZP: unimplemented_instruction(state); break;
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case STX_ZPY: unimplemented_instruction(state); break;
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case STX_ABS: unimplemented_instruction(state); break;
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case STY_ZP: unimplemented_instruction(state); break;
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case STY_ZPX: unimplemented_instruction(state); break;
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case STY_ABS: unimplemented_instruction(state); break;
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default:
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unimplemented_instruction(state); break;
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}
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17
data/generate_cpu.py
Normal file
17
data/generate_cpu.py
Normal file
@ -0,0 +1,17 @@
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import csv
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with open('cpu.c','w') as outfile:
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with open('6502_ops.csv','r') as file:
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reader = csv.DictReader(file)
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for op in reader:
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print(op)
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args = int(op['bytes'])
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addr_mode = op['addressing mode']
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suffix = '_'+ addr_mode if addr_mode != 'IMP' else ''
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mnemonic = op['mnemonic']
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name = mnemonic + suffix
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outfile.write('case %s: ' % name)
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outfile.write('unimplemented_instruction(state); break;\n')
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