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Commit Graph

34 Commits

Author SHA1 Message Date
Peter Evans
978ad1faaf Formerly "BAD" instructions are now forms of NOPs
But weird forms. In most cases they basically are NOPs, except with
different opcodes. In other cases, we call them NP2 and NP3s, and do so
because they consume 2 or 3 bytes respectively (vs. just 1 with NOP).

We had to teach some arcane magic to the emulator for this to work. We
may want to refactor to decouple the number of bytes consumed from the
address mode.
2018-02-22 14:07:05 -06:00
Peter Evans
90892c32e4 Add TSB (Test and Set Bits) instruction
This commit also moves the TRB code from loadstor to bits, which is
where it should have been all along.
2018-02-22 13:39:48 -06:00
Peter Evans
a4c3d1c4ef Implement the TRB (Test and Reset Bits) instruction 2018-02-22 00:39:33 -06:00
Peter Evans
807362e871 Add STZ instruction (to store zero) 2018-02-22 00:02:57 -06:00
Peter Evans
8e1ab0e950 Add support for PHX, PHY, PLX, PLY
These instructions allow you to push and pull (pop) the X and Y
registers via the stack.
2018-02-21 23:32:57 -06:00
Peter Evans
f9a277e7bc Add new Branch Always instruction 2018-02-21 21:57:21 -06:00
Peter Evans
7b65dc1657 Add new BIM instruction (BIt imMediate mode)
This is not a real instruction in the 65c02 processor; I invented it for
the sole purpose of handling the specialized logic that is performed by
BIT in IMM mode. To be fair--I can imagine this really _was_ implemented
as a "separate" instruction on the chip! But I don't know that for sure.
2018-02-21 21:01:46 -06:00
Peter Evans
ecd8a7974a Add "BAD" instruction to crash when we hit an invalid opcode 2018-01-21 12:48:34 -06:00
Peter Evans
0581ed6b44 Fix stack in several ways
1. The stack should descend, not ascend;
2. The stack should be pushed byte for byte; meaning, when pushing P or
A, those should consume one byte, not two;
3. The MSB should be pushed first when doing JSR and BRK, which makes
some sense if you were reading the stack from $0100 - $01FF.
2018-01-21 01:09:42 -06:00
Peter Evans
2f777ce881 Several core changes to status, soft switches
Regarding soft switches, we had several we should have been listening
for on both reads and writes, but were only doing so on writes; this is
now fixed.

Regarding statuses, we were incorrectly calculating both carry and
overflow. This should now be fixed, although some quick examinations of
disassembly output suggest there is something else amiss. Debugging will
continue shortly.
2018-01-20 21:01:26 -06:00
Peter Evans
6b160c6ca2 Show the dereferenced value for a given address 2018-01-19 12:18:24 -06:00
Peter Evans
f69454c965 Some soft switches now require consecutive reads
To allow this to work, we had to allow the CPU struct to record what the
last opcode/operand/address were, although in truth we only needed the
last address.
2018-01-12 14:49:27 -06:00
Peter Evans
7d6886a3a8 Change last_addr field to eff_addr 2018-01-12 13:57:48 -06:00
Peter Evans
9564f86a57 Remove flash_memory function 2018-01-11 21:57:52 -06:00
Peter Evans
578e0b291c Allow us to switch main/aux; write bank switch mappers 2018-01-11 19:52:13 -06:00
Peter Evans
8d9b48912e Add memory injection to 6502; main memory in apple2
Note that memory _is_ now managed in apple2, and _not_ in mos6502.
2018-01-10 21:28:05 -06:00
Peter Evans
a785eb5665 Remove next_byte, read_byte; remove opcode from execute
The execute function should just work from the PC register. It might
seem to be easier to test by passing an arbitrary opcode into the
function, but because so much of the chip's execution is
context-sensitive (that is, it expects PC to be pointing at the opcode,
to have its operand in front of it, etc.), passing an arbitrary opcode
is not really reflective of what needs to be in place for the function
to work correctly.
2018-01-09 20:56:11 -06:00
Peter Evans
1de1e7788a Rename status flags to MOS_ 2018-01-05 14:18:39 -06:00
Peter Evans
f70f21789b Add flash memory, disassemble options 2017-12-31 15:50:59 -06:00
Peter Evans
26529f77ab Implement jump table, labels in code 2017-12-29 17:08:25 -06:00
Peter Evans
89a6161272 Reorganize header files 2017-12-26 16:47:34 -06:00
Peter Evans
ea2b68dc8c Documentation, and reorganizing macro definitions 2017-12-06 21:29:03 -06:00
Peter Evans
4af7e4444c This macro was no longer needed 2017-12-06 21:26:09 -06:00
Peter Evans
00ff9f069d Vastly simplify unit tests for mos6502
Criterion's init and fini config options allow us to register setup and
teardown functions. We now use this to register the common cpu variable
for the mos6502 tests, albeit through the use of a global variable.

Doing so necessitated that each of the different test files have their
own suites, due to some implementation details in Criterion, but this is
No Big Deal.
2017-12-06 15:57:15 -06:00
Peter Evans
89ddd20658 Add read_byte function to return the next byte in memory 2017-12-05 20:40:35 -06:00
Peter Evans
50a84b4099 Remove cycles field from mos6502 struct
It was both unused and not necessary, as we can simply compute the
number of cycles in the execute function.
2017-12-05 20:23:17 -06:00
Peter Evans
eaa6c85fe4 Add the type for the execute function 2017-12-05 19:03:40 -06:00
Peter Evans
4e6073cf2e Add function decl for the execute func 2017-12-05 19:03:02 -06:00
Peter Evans
631451afe5 Use C-style to denote documentation 2017-12-05 18:40:40 -06:00
Peter Evans
8454d1a6c9 Add instruction handler function, handler table 2017-12-05 18:38:36 -06:00
Peter Evans
54473be302 Add functions for instructions, cycles, and address modes.
This also adds a new table for cycles, and adds unit test functions for
the work as well.
2017-12-04 23:30:18 -06:00
Peter Evans
87de0a877a Add all our tests, plus other fixes 2017-12-03 20:19:17 -06:00
Peter Evans
fe9ce3aca3 Tests for the new mos6502 functions 2017-12-02 13:27:30 -06:00
Peter Evans
3cebed2377 Adding all of the instruction files 2017-12-02 13:05:53 -06:00