Peter Evans
b239cac239
Add dblock command to disassemble blocks of code
2018-03-01 19:31:56 -06:00
Peter Evans
f8bda4ebd3
Remove modify_status() function
...
Also rewrite tests to use macros
2018-02-28 21:40:52 -06:00
Peter Evans
49199eac84
Rewrite status checks with macros
...
This also forces the result of operations to be considered purely as
8-bit results in _some_ cases, but not in others. We were missing some
times when an overflow is the expected behavior; because SET_RESULT()
and mos6502_modify_status() use ints, this overflow was not properly
observed.
2018-02-28 21:16:39 -06:00
Peter Evans
edd175c1f9
Add disasm command (toggle disassembly)
2018-02-26 20:52:13 -06:00
Peter Evans
4b4e58089b
Add missing function decls
2018-02-26 18:53:59 -06:00
Peter Evans
e50fda62be
Add step command
2018-02-25 15:41:37 -06:00
Peter Evans
01f230dc85
Add unbreak command, unbreak_all() function for testing
2018-02-25 14:38:24 -06:00
Peter Evans
588362abee
Add prompt; quit command; breakpoints
2018-02-25 14:25:02 -06:00
Peter Evans
09f7152e07
Add writeaddr command
2018-02-24 19:38:04 -06:00
Peter Evans
06bf63ecb2
Add jump debug command
2018-02-24 19:36:02 -06:00
Peter Evans
1be1abc0af
Add printaddr, printstate
2018-02-24 18:57:00 -06:00
Peter Evans
ec253905ad
Add resume command, finder function, arg parser, execute
2018-02-24 16:30:46 -06:00
Peter Evans
a614c1e5df
Add new file, vm_debug.c, and help command for it
2018-02-23 21:58:30 -06:00
Peter Evans
0d1e22a348
Add support for decimal mode ADC/SBC.
...
This also corrects a bug where SBC set carry incorrectly in binary mode.
2018-02-23 00:46:07 -06:00
Peter Evans
978ad1faaf
Formerly "BAD" instructions are now forms of NOPs
...
But weird forms. In most cases they basically are NOPs, except with
different opcodes. In other cases, we call them NP2 and NP3s, and do so
because they consume 2 or 3 bytes respectively (vs. just 1 with NOP).
We had to teach some arcane magic to the emulator for this to work. We
may want to refactor to decouple the number of bytes consumed from the
address mode.
2018-02-22 14:07:05 -06:00
Peter Evans
90892c32e4
Add TSB (Test and Set Bits) instruction
...
This commit also moves the TRB code from loadstor to bits, which is
where it should have been all along.
2018-02-22 13:39:48 -06:00
Peter Evans
a4c3d1c4ef
Implement the TRB (Test and Reset Bits) instruction
2018-02-22 00:39:33 -06:00
Peter Evans
807362e871
Add STZ instruction (to store zero)
2018-02-22 00:02:57 -06:00
Peter Evans
8e1ab0e950
Add support for PHX, PHY, PLX, PLY
...
These instructions allow you to push and pull (pop) the X and Y
registers via the stack.
2018-02-21 23:32:57 -06:00
Peter Evans
f9a277e7bc
Add new Branch Always instruction
2018-02-21 21:57:21 -06:00
Peter Evans
7b65dc1657
Add new BIM instruction (BIt imMediate mode)
...
This is not a real instruction in the 65c02 processor; I invented it for
the sole purpose of handling the specialized logic that is performed by
BIT in IMM mode. To be fair--I can imagine this really _was_ implemented
as a "separate" instruction on the chip! But I don't know that for sure.
2018-02-21 21:01:46 -06:00
Peter Evans
61eb880f49
Refactor code to pass image type in
2018-02-21 00:23:12 -06:00
Peter Evans
1091ec6e2a
Pass image type into enc_dos; use sector_num instead of a table pointer
2018-02-20 15:36:23 -06:00
Peter Evans
98f640f0d1
Use the proper sector header length (20 bytes)
2018-02-20 14:35:07 -06:00
Peter Evans
508be6458a
Pass in sector table for logical-physical orders
...
We were not encoding data properly, because in DOS 3.3 and ProDOS,
sectors must be interleaved on disk media (whereas in the original image
form, data is laid out in a linear fashion).
This solves a bug where we erroneously encountered a "bad" opcode (a7)
in the program code.
2018-02-19 18:49:37 -06:00
Peter Evans
96e4b5d9d8
Remove JSR WAIT to speed up disk II controller
2018-02-19 00:48:11 -06:00
Peter Evans
c89e855559
Update to use correct encoded sector length
2018-02-18 23:46:18 -06:00
Peter Evans
3223fe6110
Enable disassembly toggle (ALT+D)
2018-02-07 15:24:02 -06:00
Peter Evans
308a1070ae
Add paused field, pause execution
2018-02-07 14:44:04 -06:00
Peter Evans
433d9a436f
Add pause function, flesh out machine_info
2018-02-07 14:43:20 -06:00
Peter Evans
a84b4c12e9
Treat pause and disasm as toggle functions
...
This allows us to remove the resume and disasm_off functions. (The
disasm_on function is simply renamed to disasm.)
2018-02-07 14:41:44 -06:00
Peter Evans
360e9243f8
Use the DI container to get machine/cpu/etc
2018-02-07 00:02:20 -06:00
Peter Evans
c35a6cb827
Add VM_OUTPUT DI entry
2018-02-07 00:01:57 -06:00
Peter Evans
09017aa171
Use DI to obtain the reflect struct
2018-02-07 00:01:27 -06:00
Peter Evans
4e0892dc86
Add dependency injection container for vm
2018-02-06 23:24:48 -06:00
Peter Evans
608b2259e5
Break keyboard event logic out into normal/special
2018-02-06 16:29:15 -06:00
Peter Evans
a388cf0158
Add missing param name for reflect struct
2018-02-06 14:26:57 -06:00
Peter Evans
fbee851daf
Add apple2 reflect code
2018-02-06 00:30:46 -06:00
Peter Evans
b7f2cabb3e
Add new REFLECT macro to allow other code to define funcs
2018-02-05 21:55:13 -06:00
Peter Evans
c1c42834ed
Add reflect system to virtual machine
2018-02-05 20:31:05 -06:00
Peter Evans
92ee67c8d8
Allow us to signal that we should exit
2018-02-05 00:35:04 -06:00
Peter Evans
72c4111458
Add event system; move event code into vm_event.c
2018-02-05 00:28:22 -06:00
Peter Evans
7212a1041a
Encoded tracks should be longer
2018-02-04 15:41:48 -06:00
Peter Evans
4777886d2d
Add missing decl for phaser
2018-02-04 00:26:01 -06:00
Peter Evans
8009a33bd4
Use int return for error code
2018-02-04 00:06:22 -06:00
Peter Evans
dd2b956b49
Add ERR_INVALID error code
2018-02-04 00:06:04 -06:00
Peter Evans
a970759bec
Add missing extern for the save function
2018-02-03 21:17:54 -06:00
Peter Evans
a6c1564747
Add fwrite function, support for streams and types
2018-02-03 20:50:08 -06:00
Peter Evans
2dd21f1487
Add image type, image segment
2018-02-03 18:10:29 -06:00
Peter Evans
5fc0206ff6
Add defines for track/sector sizes
2018-02-03 00:24:22 -06:00
