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fix disassembler address display
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Irmen de Jong
parent
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commit
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2
LICENSE
2
LICENSE
@ -1,6 +1,6 @@
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MIT License
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Copyright (c) 2016 Irmen de Jong
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Copyright (c) 2019 Irmen de Jong
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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23
README.md
23
README.md
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[](https://saythanks.io/to/irmen)
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[](https://travis-ci.org/irmen/ksim65)
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KSim65 - Kotlin 6502/65C02 microprocessor simulator
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===================================================
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# KSim65 - Kotlin/JVM 6502/65C02 microprocessor simulator
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*Written by Irmen de Jong (irmen@razorvine.net)*
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@ -11,8 +10,20 @@ KSim65 - Kotlin 6502/65C02 microprocessor simulator
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This is a Kotlin library to simulate the 8-bit 6502 and 65C02 microprocessors of the early 80's.
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This is a Kotlin/JVM library that simulates the 8-bit 6502 and 65C02 microprocessors,
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which became very popular in the the early 1980's.
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The simulation is cycle precise, includes BCD mode, and all opcodes are implemented (including the 'illegal' opcodes of the 6502).
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On my machine the library can simulate a 6502 running at up to ~100Mhz.
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Properties of this simulator:
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- Written in Kotlin. It is low-level code, but hopefully still readable :-)
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- Designed to simulate hardware components (bus, cpu, memory, i/o controllers)
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- IRQ and NMI simulation
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- Aims to be clock cycle-precise (not yet 100% correct right now)
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- Aims to implements all 6502 and 65c02 instructions, including the 'illegal' 6502 instructions (not yet done)
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- correct BCD mode for adc/sbc instructions on both cpu types
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- passes several extensive unit test suites that verify instruction and cpu flags behavior
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- maximum simulated performance is a 6502 running at ~100 Mhz (on my machine)
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## Documentation
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Still to be written. For now,
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@ -14,7 +14,7 @@ fun main(args: Array<String>) {
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internal fun printSoftwareHeader() {
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val buildVersion = object {}.javaClass.getResource("/version.txt").readText().trim()
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println("\nKSim65 6502 cpu simulator v$buildVersion by Irmen de Jong (irmen@razorvine.net)")
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println("This software is licensed under the GNU GPL 3.0, see https://www.gnu.org/licenses/gpl.html\n")
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println("This software is free and licensed under the MIT open-source license\n")
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}
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@ -70,8 +70,7 @@ private fun startSimulator(args: Array<String>) {
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bus.clock()
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}
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} catch (ix: Cpu6502.InstructionError) {
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println("HMMM $ix")
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// ignore
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println("Hmmm... $ix")
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}
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ram.hexDump(0x1000, 0x1020)
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@ -133,16 +133,16 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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disassemble(component.cloneContents(), component.startAddress, from, to)
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fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address): List<String> {
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var address = from - baseAddress
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var location = from - baseAddress
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val spacing1 = " "
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val spacing2 = " "
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val spacing3 = " "
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val result = mutableListOf<String>()
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while (address <= (to - baseAddress)) {
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val byte = memory[address]
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var line = "\$${hexW(address)} ${hexB(byte)} "
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address++
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while (location <= (to - baseAddress)) {
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val byte = memory[location]
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var line = "\$${hexW(location+baseAddress)} ${hexB(byte)} "
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location++
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val opcode = instructions[byte.toInt()]
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when (opcode.mode) {
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AddrMode.Acc -> {
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@ -152,83 +152,83 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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line += "$spacing1 ${opcode.mnemonic}"
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}
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AddrMode.Imm -> {
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val value = memory[address++]
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val value = memory[location++]
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line += "${hexB(value)} $spacing2 ${opcode.mnemonic} #\$${hexB(value)}"
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}
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AddrMode.Zp -> {
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val zpAddr = memory[address++]
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val zpAddr = memory[location++]
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}"
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}
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AddrMode.Zpr -> {
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// addressing mode used by the 65C02, put here for convenience
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val zpAddr = memory[address++]
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val rel = memory[address++]
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val zpAddr = memory[location++]
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val rel = memory[location++]
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val target =
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if (rel <= 0x7f)
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address + rel
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location + rel + baseAddress
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else
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address - (256 - rel)
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location - (256 - rel) + baseAddress
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line += "${hexB(zpAddr)} ${hexB(rel)} $spacing3 ${opcode.mnemonic} \$${hexB(zpAddr)}, \$${hexW(target, true)}"
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}
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AddrMode.Izp -> {
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// addressing mode used by the 65C02, put here for convenience
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val zpAddr = memory[address++]
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val zpAddr = memory[location++]
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$(${hexB(zpAddr)})"
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}
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AddrMode.IaX -> {
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// addressing mode used by the 65C02, put here for convenience
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val lo = memory[address++]
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val hi = memory[address++]
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val lo = memory[location++]
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val hi = memory[location++]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$(${hexW(absAddr)},x)"
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}
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AddrMode.ZpX -> {
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val zpAddr = memory[address++]
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val zpAddr = memory[location++]
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},x"
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}
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AddrMode.ZpY -> {
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val zpAddr = memory[address++]
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val zpAddr = memory[location++]
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},y"
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}
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AddrMode.Rel -> {
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val rel = memory[address++]
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val rel = memory[location++]
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val target =
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if (rel <= 0x7f)
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address + rel
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location + rel + baseAddress
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else
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address - (256 - rel)
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location - (256 - rel) + baseAddress
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line += "${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target, true)}"
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}
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AddrMode.Abs -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val lo = memory[location++]
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val hi = memory[location++]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)}"
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}
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AddrMode.AbsX -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val lo = memory[location++]
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val hi = memory[location++]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},x"
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}
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AddrMode.AbsY -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val lo = memory[location++]
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val hi = memory[location++]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},y"
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}
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AddrMode.Ind -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val lo = memory[location++]
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val hi = memory[location++]
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val indirectAddr = lo.toInt() or (hi.toInt() shl 8)
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} (\$${hexW(indirectAddr)})"
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}
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AddrMode.IzX -> {
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val zpAddr = memory[address++]
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val zpAddr = memory[location++]
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)},x)"
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}
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AddrMode.IzY -> {
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val zpAddr = memory[address++]
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val zpAddr = memory[location++]
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)}),y"
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}
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}
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@ -1,5 +1,6 @@
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import razorvine.ksim65.components.Bus
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import razorvine.ksim65.components.Cpu6502
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import razorvine.ksim65.components.Cpu65C02
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import razorvine.ksim65.components.Ram
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import kotlin.test.*
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import kotlin.system.measureNanoTime
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@ -9,7 +10,7 @@ import kotlin.test.assertEquals
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class Test6502CpuBasics {
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@Test
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fun testCpuFlagsAfterReset() {
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fun testCpuFlagsAfterReset6502() {
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val cpu = Cpu6502(true)
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val bus = Bus()
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bus.add(cpu)
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@ -27,7 +28,25 @@ class Test6502CpuBasics {
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}
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@Test
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fun testCpuPerformance() {
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fun testCpuFlagsAfterReset65c02() {
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val cpu = Cpu65C02(true)
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val bus = Bus()
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bus.add(cpu)
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cpu.reset()
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assertEquals(0xfd, cpu.SP)
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assertEquals(0xffff, cpu.PC)
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assertEquals(0, cpu.totalCycles)
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assertEquals(8, cpu.instrCycles)
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assertEquals(0, cpu.A)
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assertEquals(0, cpu.X)
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assertEquals(0, cpu.Y)
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assertEquals(0, cpu.currentOpcode)
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assertEquals(Cpu6502.StatusRegister(C = false, Z = false, I = true, D = false, B = false, V = false, N = false), cpu.Status)
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assertEquals(0b00100100, cpu.Status.asByte())
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}
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@Test
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fun testCpuPerformance6502() {
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val cpu = Cpu6502(true)
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val ram = Ram(0x1000, 0x2000)
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// load a simple program that loops a few instructions
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@ -58,14 +77,46 @@ class Test6502CpuBasics {
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}
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@Test
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fun testBCD() {
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fun testCpuPerformance65C02() {
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val cpu = Cpu65C02(true)
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val ram = Ram(0x0000, 0x2000)
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// load a simple program that loops a few instructions
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for(b in listOf(0xa9, 0x63, 0xaa, 0x86, 0x22, 0x8e, 0x22, 0x22, 0x91, 0x22, 0x6d, 0x33, 0x33, 0xcd, 0x55, 0x55,
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0xff, 0xff, 0x79, 0x9e, 0x56, 0x34, 0xd0, 0xe8, 0xf0, 0xe6).withIndex()) {
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ram[0x1000+b.index] = b.value.toShort()
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}
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val bus = Bus()
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bus.add(cpu)
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bus.add(ram)
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cpu.reset()
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cpu.PC = 0x1000
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// warmup
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while(cpu.totalCycles<5000000)
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cpu.clock()
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// timing
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val cycles = 100000000
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val duration = measureNanoTime {
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while (cpu.totalCycles < cycles)
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cpu.clock()
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}
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val seconds = duration.toDouble() / 1e9
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val mhz = (cycles.toDouble() / seconds) / 1e6
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println("duration $seconds sec for $cycles = $mhz Mhz")
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}
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@Test
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fun testBCD6502() {
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val cpu = Cpu6502(true)
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val bus = Bus()
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bus.add(cpu)
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val ram = Ram(0, 0xffff)
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ram[Cpu6502.RESET_vector] = 0x00
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ram[Cpu6502.RESET_vector +1] = 0x10
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val bytes = javaClass.getResource("bcdtest.bin")!!
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val bytes = javaClass.getResource("bcdtest6502.bin")!! // only works on 6502, not on the 65c02
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ram.load(bytes, 0x1000)
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bus.add(ram)
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bus.reset()
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@ -79,7 +130,7 @@ class Test6502CpuBasics {
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}
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if(ram[0x0400] ==0.toShort()) {
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println("BCD TEST: OK!")
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println("BCD TEST for 6502: OK!")
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}
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else {
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val code = ram[0x0400]
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@ -75,23 +75,23 @@ ${'$'}0050 00 brk""", result)
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val cpu = Cpu65C02()
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val memory = Ram(0, 0x1000)
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val source = javaClass.classLoader.getResource("disassem_wdc65c02.bin")!!
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memory.load(source, 0)
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val resultLines = cpu.disassemble(memory, 0x0000, 0x0015)
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memory.load(source, 0x200)
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val resultLines = cpu.disassemble(memory, 0x0200, 0x0215)
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val result = resultLines.joinToString("\n")
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assertEquals("""${'$'}0000 cb wai
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${'$'}0001 db stp
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${'$'}0002 3a dec a
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${'$'}0003 1a inc a
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${'$'}0004 64 12 stz ${'$'}12
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${'$'}0006 14 12 trb ${'$'}12
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${'$'}0008 04 12 tsb ${'$'}12
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${'$'}000a 72 12 adc ${'$'}(12)
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${'$'}000c b2 12 lda ${'$'}(12)
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${'$'}000e 92 12 sta ${'$'}(12)
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${'$'}0010 7c 00 20 jmp ${'$'}(2000,x)
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${'$'}0013 00 brk
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${'$'}0014 00 brk
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${'$'}0015 00 brk""", result)
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assertEquals("""${'$'}0200 cb wai
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${'$'}0201 db stp
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${'$'}0202 3a dec a
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${'$'}0203 1a inc a
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${'$'}0204 64 12 stz ${'$'}12
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${'$'}0206 14 12 trb ${'$'}12
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${'$'}0208 04 12 tsb ${'$'}12
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${'$'}020a 72 12 adc ${'$'}(12)
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${'$'}020c b2 12 lda ${'$'}(12)
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${'$'}020e 92 12 sta ${'$'}(12)
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${'$'}0210 7c 00 20 jmp ${'$'}(2000,x)
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${'$'}0213 00 brk
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${'$'}0214 00 brk
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${'$'}0215 00 brk""", result)
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}
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}
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