mirror of
https://github.com/irmen/ksim65.git
synced 2024-05-29 03:41:30 +00:00
cleanups
This commit is contained in:
Irmen de Jong
parent
66c4033eb4
commit
84831adb07
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@ -1,5 +1,6 @@
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import org.jetbrains.dokka.gradle.DokkaTask
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import org.jetbrains.kotlin.gradle.tasks.KotlinCompile
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import kotlin.math.max
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plugins {
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// Apply the Kotlin JVM plugin to add support for Kotlin on the JVM.
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@ -46,9 +47,9 @@ tasks.named<Test>("test") {
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testLogging.events("failed")
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// parallel tests.
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systemProperties["junit.jupiter.execution.parallel.enabled"] = true
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systemProperties["junit.jupiter.execution.parallel.mode.default"] = "concurrent"
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maxParallelForks = Runtime.getRuntime().availableProcessors() / 2
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systemProperty("junit.jupiter.execution.parallel.enabled", "true")
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systemProperty("junit.jupiter.execution.parallel.mode.default", "concurrent")
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maxParallelForks = max(1, Runtime.getRuntime().availableProcessors() / 2)
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}
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tasks.withType<KotlinCompile>().all {
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@ -65,13 +65,14 @@ private fun startSimulator(args: Array<String>) {
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cpu.Status.I = false // enable interrupts
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try {
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while (true) {
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bus.clock()
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}
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} catch (ix: Cpu6502.InstructionError) {
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println("Hmmm... $ix")
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}
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// TODO
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// try {
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// while (true) {
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// bus.clock()
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// }
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// } catch (ix: Cpu6502.InstructionError) {
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// println("Hmmm... $ix")
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// }
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ram.hexDump(0x1000, 0x1020)
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val dis = cpu.disassemble(ram, 0x1000, 0x1020)
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File diff suppressed because it is too large
Load Diff
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@ -1,7 +1,5 @@
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package razorvine.ksim65.components
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import razorvine.ksim65.c64.Petscii
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typealias UByte = Short
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typealias Address = Int
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@ -22,7 +20,7 @@ abstract class MemMappedComponent(val startAddress: Address, val endAddress: Add
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require(startAddress >= 0 && endAddress <= 0xffff) { "can only have 16-bit address space" }
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}
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fun hexDump(from: Address, to: Address) {
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fun hexDump(from: Address, to: Address, charmapper: ((Short)->Char)? = null) {
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(from..to).chunked(16).forEach {
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print("\$${it.first().toString(16).padStart(4, '0')} ")
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val bytes = it.map { address -> get(address) }
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@ -30,8 +28,12 @@ abstract class MemMappedComponent(val startAddress: Address, val endAddress: Add
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print(byte.toString(16).padStart(2, '0') + " ")
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}
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print(" ")
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print(Petscii.decodeScreencode(bytes, false).replace('\ufffe', '.'))
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println()
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val chars =
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if(charmapper!=null)
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bytes.map { b -> charmapper(b) }
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else
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bytes.map { b -> if(b in 32..255) b.toChar() else '.' }
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println(chars.joinToString(""))
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}
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}
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}
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@ -7,7 +7,7 @@ package razorvine.ksim65.components
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* TODO: add the optional additional cycles to certain instructions and addressing modes
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*/
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open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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var tracing: Boolean = false
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var tracing: ((state:String) -> Unit)? = null
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var totalCycles: Long = 0
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protected set
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@ -20,7 +20,7 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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const val resetCycles = 8
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}
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enum class AddrMode {
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protected enum class AddrMode {
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Imp,
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Acc,
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Imm,
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@ -39,8 +39,6 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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IaX, // special addressing mode used by the 65C02
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}
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class Instruction(val mnemonic: String, val mode: AddrMode, val cycles: Int)
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class StatusRegister(
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var C: Boolean = false,
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var Z: Boolean = false,
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@ -85,8 +83,9 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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}
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}
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protected class Instruction(val mnemonic: String, val mode: AddrMode, val cycles: Int)
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var instrCycles: Int = 0
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var A: Int = 0
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var X: Int = 0
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var Y: Int = 0
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@ -94,24 +93,32 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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var PC: Address = 0
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val Status = StatusRegister()
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var currentOpcode: Int = 0
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protected set
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var instrCycles: Int = 0
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protected set
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protected lateinit var currentInstruction: Instruction
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// has an interrupt been requested?
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protected var pendingInterrupt: Pair<Boolean, BusComponent>? = null
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// data byte from the instruction (only set when addr.mode is Accumulator, Immediate or Implied)
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private var fetchedData: Int = 0
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protected var fetchedData: Int = 0
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// all other addressing modes yield a fetched memory address
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protected var fetchedAddress: Address = 0
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private val breakpoints = mutableMapOf<Address, (cpu: Cpu6502, pc: Address) -> Unit>()
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class BreakpointResult(val newPC: Address?, val newOpcode: Int?)
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fun breakpoint(address: Address, action: (cpu: Cpu6502, pc: Address) -> Unit) {
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private val breakpoints = mutableMapOf<Address, (cpu: Cpu6502, pc: Address) -> BreakpointResult>()
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fun addBreakpoint(address: Address, action: (cpu: Cpu6502, pc: Address) -> BreakpointResult) {
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breakpoints[address] = action
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}
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internal fun hexW(number: Address, allowSingleByte: Boolean = false): String {
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fun removeBreakpoint(address: Address) = breakpoints.remove(address)
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fun hexW(number: Address, allowSingleByte: Boolean = false): String {
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val msb = number ushr 8
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val lsb = number and 0xff
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return if (msb == 0 && allowSingleByte)
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@ -120,9 +127,9 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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hexB(msb) + hexB(lsb)
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}
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internal fun hexB(number: Short): String = hexB(number.toInt())
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fun hexB(number: Short): String = hexB(number.toInt())
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internal fun hexB(number: Int): String {
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fun hexB(number: Int): String {
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val hexdigits = "0123456789abcdef"
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val loNibble = number and 15
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val hiNibble = number ushr 4
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@ -268,16 +275,19 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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currentOpcode = read(PC)
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currentInstruction = instructions[currentOpcode]
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if (tracing) printState()
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tracing?.invoke(logState())
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breakpoints[PC]?.let {
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breakpoints[PC]?.let { breakpoint ->
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val oldPC = PC
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val oldOpcode = currentOpcode
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it(this, PC)
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val result = breakpoint(this, PC)
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if(result.newPC!=null)
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PC = result.newPC
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if (PC != oldPC)
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return clock()
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if (oldOpcode != currentOpcode)
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else if(result.newOpcode!=null) {
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currentOpcode = result.newOpcode
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currentInstruction = instructions[currentOpcode]
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}
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}
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if (stopOnBrk && currentOpcode == 0) {
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@ -311,9 +321,8 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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pendingInterrupt = Pair(false, source)
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}
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fun printState() {
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println(
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"cycle:$totalCycles - pc=${hexW(PC)} " +
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fun logState(): String =
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"cycle:$totalCycles - pc=${hexW(PC)} " +
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"A=${hexB(A)} " +
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"X=${hexB(X)} " +
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"Y=${hexB(Y)} " +
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@ -326,8 +335,6 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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" z=" + (if (Status.Z) "1" else "0") +
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" c=" + (if (Status.C) "1" else "0") +
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" icycles=$instrCycles instr=${hexB(currentOpcode)}:${currentInstruction.mnemonic}"
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)
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}
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protected fun getFetched() =
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if (currentInstruction.mode == AddrMode.Imm ||
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@ -361,7 +368,7 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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return read(SP or 0x0100)
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}
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private fun popStackAddr(): Address {
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protected fun popStackAddr(): Address {
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val lo = popStack()
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val hi = popStack()
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return lo or (hi shl 8)
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@ -1,14 +1,12 @@
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package razorvine.ksim65.components
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import razorvine.ksim65.c64.Petscii
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/**
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* A parallel output device (basically, prints bytes as characters to the screen)
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* First address = data byte (8 parallel bits)
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* Second address = control byte (bit 0 high = write byte)
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*/
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class ParallelPort(startAddress: Address, endAddress: Address) : MemMappedComponent(startAddress, endAddress) {
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var dataByte: UByte = 0
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private var dataByte: UByte = 0
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init {
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require(endAddress - startAddress + 1 == 2) { "parallel needs exactly 2 memory bytes (data + control)" }
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@ -29,7 +27,7 @@ class ParallelPort(startAddress: Address, endAddress: Address) : MemMappedCompon
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dataByte = data
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else if (address == endAddress) {
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if ((data.toInt() and 1) == 1) {
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val char = Petscii.decodeScreencode(listOf(dataByte), false).first()
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val char = dataByte.toChar()
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println("PARALLEL WRITE: '$char'")
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}
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}
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@ -1,4 +1,3 @@
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import razorvine.ksim65.c64.Petscii
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import razorvine.ksim65.components.Address
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import razorvine.ksim65.components.Cpu6502
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import razorvine.ksim65.components.Ram
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@ -6,17 +5,17 @@ import razorvine.ksim65.components.Ram
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class C64KernalStubs(private val ram: Ram) {
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fun handleBreakpoint(cpu: Cpu6502, pc: Address) {
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fun handleBreakpoint(cpu: Cpu6502, pc: Address): Cpu6502.BreakpointResult {
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when(pc) {
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0xffd2 -> {
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// CHROUT
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ram[0x030c] = 0
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val char = Petscii.decodePetscii(listOf(cpu.A.toShort()), true).first()
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val char = cpu.A.toChar()
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if(char==13.toChar())
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println()
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else if(char in ' '..'~')
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print(char)
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cpu.currentOpcode = 0x60 // rts to end the stub
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return Cpu6502.BreakpointResult(null, 0x60) // perform an RTS to exit this subroutine
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}
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0xffe4 -> {
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// GETIN
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@ -40,6 +39,8 @@ class C64KernalStubs(private val ram: Ram) {
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// cpu.PC = 0x0816 // continue in next module
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}
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}
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return Cpu6502.BreakpointResult(null, null)
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}
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}
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@ -20,10 +20,11 @@ class Test6502Functional {
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bus.add(ram)
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cpu.reset()
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cpu.PC = 0x0400
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cpu.breakpoint(0x3469) { _, _ ->
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cpu.addBreakpoint(0x3469) { _, _ ->
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// reaching this address means successful test result
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if(cpu.currentOpcode==0x4c)
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throw SuccessfulTestResult()
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Cpu6502.BreakpointResult(null, null)
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}
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try {
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@ -35,7 +36,7 @@ class Test6502Functional {
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return
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}
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cpu.printState()
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println(cpu.logState())
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val d = cpu.disassemble(ram, cpu.PC-20, cpu.PC+20)
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println(d.joinToString ("\n"))
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fail("test failed")
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@ -51,10 +52,11 @@ class Test6502Functional {
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bus.add(ram)
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cpu.reset()
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cpu.PC = 0x0400
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cpu.breakpoint(0x24f1) { _, _ ->
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cpu.addBreakpoint(0x24f1) { _, _ ->
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// reaching this address means successful test result
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if(cpu.currentOpcode==0x4c)
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throw SuccessfulTestResult()
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Cpu6502.BreakpointResult(null, null)
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}
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try {
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@ -66,7 +68,7 @@ class Test6502Functional {
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return
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}
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cpu.printState()
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println(cpu.logState())
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val d = cpu.disassemble(ram, cpu.PC-20, cpu.PC+20)
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println(d.joinToString ("\n"))
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fail("test failed")
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@ -7,7 +7,7 @@ import kotlin.test.*
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@TestInstance(TestInstance.Lifecycle.PER_METHOD)
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@Disabled("this test suite takes a long time")
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// @Disabled("this test suite takes a long time")
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class Test6502TestSuite {
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val cpu: Cpu6502 = Cpu6502(stopOnBrk = false)
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@ -16,10 +16,10 @@ class Test6502TestSuite {
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val kernalStubs = C64KernalStubs(ram)
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init {
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cpu.tracing = false
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cpu.breakpoint(0xffd2) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.breakpoint(0xffe4) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.breakpoint(0xe16f) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.tracing = null
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cpu.addBreakpoint(0xffd2) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.addBreakpoint(0xffe4) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.addBreakpoint(0xe16f) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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// create the system bus and add device to it.
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// note that the order is relevant w.r.t. where reads and writes are going.
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@ -54,7 +54,7 @@ class Test6502TestSuite {
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while (cpu.totalCycles < 50000000L) {
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bus.clock()
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}
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fail("test hangs")
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fail("test hangs: " + cpu.logState())
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} catch (e: Cpu6502.InstructionError) {
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println(">>> INSTRUCTION ERROR: ${e.message}")
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} catch (le: KernalLoadNextPart) {
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|
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@ -30,44 +30,44 @@ class TestDisassembler {
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val cpu = Cpu65C02()
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val memory = Ram(0, 0x1000)
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val source = javaClass.classLoader.getResource("disassem_r65c02.bin")!!
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memory.load(source, 0)
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val resultLines = cpu.disassemble(memory, 0x0000, 0x0050)
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memory.load(source, 0x0200)
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val resultLines = cpu.disassemble(memory, 0x0200, 0x0250)
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val result = resultLines.joinToString("\n")
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assertEquals("""${'$'}0000 07 12 rmb0 ${'$'}12
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${'$'}0002 17 12 rmb1 ${'$'}12
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${'$'}0004 27 12 rmb2 ${'$'}12
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${'$'}0006 37 12 rmb3 ${'$'}12
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${'$'}0008 47 12 rmb4 ${'$'}12
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${'$'}000a 57 12 rmb5 ${'$'}12
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${'$'}000c 67 12 rmb6 ${'$'}12
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${'$'}000e 77 12 rmb7 ${'$'}12
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${'$'}0010 87 12 smb0 ${'$'}12
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${'$'}0012 97 12 smb1 ${'$'}12
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${'$'}0014 a7 12 smb2 ${'$'}12
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${'$'}0016 b7 12 smb3 ${'$'}12
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${'$'}0018 c7 12 smb4 ${'$'}12
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${'$'}001a d7 12 smb5 ${'$'}12
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${'$'}001c e7 12 smb6 ${'$'}12
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${'$'}001e f7 12 smb7 ${'$'}12
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${'$'}0020 0f 12 2a bbr0 ${'$'}12, ${'$'}4d
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${'$'}0023 1f 12 27 bbr1 ${'$'}12, ${'$'}4d
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${'$'}0026 2f 12 24 bbr2 ${'$'}12, ${'$'}4d
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${'$'}0029 3f 12 21 bbr3 ${'$'}12, ${'$'}4d
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${'$'}002c 4f 12 1e bbr4 ${'$'}12, ${'$'}4d
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${'$'}002f 5f 12 1b bbr5 ${'$'}12, ${'$'}4d
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${'$'}0032 6f 12 18 bbr6 ${'$'}12, ${'$'}4d
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${'$'}0035 8f 12 15 bbs0 ${'$'}12, ${'$'}4d
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${'$'}0038 9f 12 12 bbs1 ${'$'}12, ${'$'}4d
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${'$'}003b af 12 0f bbs2 ${'$'}12, ${'$'}4d
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${'$'}003e bf 12 0c bbs3 ${'$'}12, ${'$'}4d
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${'$'}0041 cf 12 09 bbs4 ${'$'}12, ${'$'}4d
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${'$'}0044 df 12 06 bbs5 ${'$'}12, ${'$'}4d
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${'$'}0047 ef 12 03 bbs6 ${'$'}12, ${'$'}4d
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${'$'}004a ff 12 00 bbs7 ${'$'}12, ${'$'}4d
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${'$'}004d 00 brk
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${'$'}004e 00 brk
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${'$'}004f 00 brk
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${'$'}0050 00 brk""", result)
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assertEquals("""${'$'}0200 07 12 rmb0 ${'$'}12
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${'$'}0202 17 12 rmb1 ${'$'}12
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${'$'}0204 27 12 rmb2 ${'$'}12
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${'$'}0206 37 12 rmb3 ${'$'}12
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${'$'}0208 47 12 rmb4 ${'$'}12
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${'$'}020a 57 12 rmb5 ${'$'}12
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${'$'}020c 67 12 rmb6 ${'$'}12
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${'$'}020e 77 12 rmb7 ${'$'}12
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${'$'}0210 87 12 smb0 ${'$'}12
|
||||
${'$'}0212 97 12 smb1 ${'$'}12
|
||||
${'$'}0214 a7 12 smb2 ${'$'}12
|
||||
${'$'}0216 b7 12 smb3 ${'$'}12
|
||||
${'$'}0218 c7 12 smb4 ${'$'}12
|
||||
${'$'}021a d7 12 smb5 ${'$'}12
|
||||
${'$'}021c e7 12 smb6 ${'$'}12
|
||||
${'$'}021e f7 12 smb7 ${'$'}12
|
||||
${'$'}0220 0f 12 2a bbr0 ${'$'}12, ${'$'}024d
|
||||
${'$'}0223 1f 12 27 bbr1 ${'$'}12, ${'$'}024d
|
||||
${'$'}0226 2f 12 24 bbr2 ${'$'}12, ${'$'}024d
|
||||
${'$'}0229 3f 12 21 bbr3 ${'$'}12, ${'$'}024d
|
||||
${'$'}022c 4f 12 1e bbr4 ${'$'}12, ${'$'}024d
|
||||
${'$'}022f 5f 12 1b bbr5 ${'$'}12, ${'$'}024d
|
||||
${'$'}0232 6f 12 18 bbr6 ${'$'}12, ${'$'}024d
|
||||
${'$'}0235 8f 12 15 bbs0 ${'$'}12, ${'$'}024d
|
||||
${'$'}0238 9f 12 12 bbs1 ${'$'}12, ${'$'}024d
|
||||
${'$'}023b af 12 0f bbs2 ${'$'}12, ${'$'}024d
|
||||
${'$'}023e bf 12 0c bbs3 ${'$'}12, ${'$'}024d
|
||||
${'$'}0241 cf 12 09 bbs4 ${'$'}12, ${'$'}024d
|
||||
${'$'}0244 df 12 06 bbs5 ${'$'}12, ${'$'}024d
|
||||
${'$'}0247 ef 12 03 bbs6 ${'$'}12, ${'$'}024d
|
||||
${'$'}024a ff 12 00 bbs7 ${'$'}12, ${'$'}024d
|
||||
${'$'}024d 00 brk
|
||||
${'$'}024e 00 brk
|
||||
${'$'}024f 00 brk
|
||||
${'$'}0250 00 brk""", result)
|
||||
}
|
||||
|
||||
@Test
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user