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prepare for extra cycles in addrmode/instructions
This commit is contained in:
Irmen de Jong
parent
e5e41d053e
commit
ca2eede585
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@ -9,7 +9,6 @@ import razorvine.ksim65.components.UByte
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/**
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* 6502 cpu simulation (the NMOS version) including the 'illegal' opcodes.
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* TODO: actually implement the illegal opcodes, see http://www.ffd2.com/fridge/docs/6502-NMOS.extra.opcodes
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* TODO: add the optional additional cycles to certain instructions and addressing modes
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*/
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open class Cpu6502 : BusComponent() {
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open val name = "6502"
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@ -285,8 +284,10 @@ open class Cpu6502 : BusComponent() {
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regPC++
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instrCycles = currentInstruction.cycles
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applyAddressingMode(currentInstruction.mode)
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dispatchOpcode(currentOpcode)
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val extraCycleFromAddr = applyAddressingMode(currentInstruction.mode)
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val extraCycleFromInstr = dispatchOpcode(currentOpcode)
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if(extraCycleFromAddr and extraCycleFromInstr)
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instrCycles++
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}
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instrCycles--
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@ -631,45 +632,57 @@ open class Cpu6502 : BusComponent() {
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/* fe */ Instruction("inc", AddrMode.AbsX, 7),
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/* ff */ Instruction("isc", AddrMode.AbsX, 7)).toTypedArray()
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protected open fun applyAddressingMode(addrMode: AddrMode) {
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when (addrMode) {
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protected open fun applyAddressingMode(addrMode: AddrMode): Boolean {
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// an addressing mode can cause an extra clock cycle on certain instructions
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return when (addrMode) {
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AddrMode.Imp, AddrMode.Acc -> {
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fetchedData = regA
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false
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}
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AddrMode.Imm -> {
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fetchedData = readPc()
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false
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}
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AddrMode.Zp -> {
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fetchedAddress = readPc()
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false
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}
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AddrMode.ZpX -> {
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// note: zeropage index will not leave Zp when page boundary is crossed
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fetchedAddress = (readPc()+regX) and 0xff
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false
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}
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AddrMode.ZpY -> {
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// note: zeropage index will not leave Zp when page boundary is crossed
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fetchedAddress = (readPc()+regY) and 0xff
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false
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}
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AddrMode.Rel -> {
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val relative = readPc()
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fetchedAddress = if (relative >= 0x80) {
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regPC-(256-relative) and 0xffff
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} else regPC+relative and 0xffff
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false
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}
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AddrMode.Abs -> {
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val lo = readPc()
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val hi = readPc()
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fetchedAddress = lo or (hi shl 8)
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false
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}
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AddrMode.AbsX -> {
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val lo = readPc()
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val hi = readPc()
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fetchedAddress = regX+(lo or (hi shl 8)) and 0xffff
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// if this address is a different page, extra clock cycle:
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(fetchedAddress and 0xff00) != hi shl 8
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}
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AddrMode.AbsY -> {
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val lo = readPc()
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val hi = readPc()
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fetchedAddress = regY+(lo or (hi shl 8)) and 0xffff
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// if this address is a different page, extra clock cycle:
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(fetchedAddress and 0xff00) != hi shl 8
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}
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AddrMode.Ind -> {
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var lo = readPc()
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@ -686,6 +699,7 @@ open class Cpu6502 : BusComponent() {
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hi = read(fetchedAddress+1)
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}
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fetchedAddress = lo or (hi shl 8)
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false
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}
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AddrMode.IzX -> {
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// note: not able to fetch an address which crosses the (zero)page boundary
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@ -693,6 +707,7 @@ open class Cpu6502 : BusComponent() {
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val lo = read((fetchedAddress+regX) and 0xff)
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val hi = read((fetchedAddress+regX+1) and 0xff)
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fetchedAddress = lo or (hi shl 8)
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false
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}
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AddrMode.IzY -> {
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// note: not able to fetch an address which crosses the (zero)page boundary
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@ -700,6 +715,7 @@ open class Cpu6502 : BusComponent() {
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val lo = read(fetchedAddress)
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val hi = read((fetchedAddress+1) and 0xff)
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fetchedAddress = regY+(lo or (hi shl 8)) and 0xffff
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false
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}
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AddrMode.Zpr, AddrMode.Izp, AddrMode.IaX -> {
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// addressing mode used by the 65C02 only
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@ -708,7 +724,7 @@ open class Cpu6502 : BusComponent() {
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}
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}
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protected open fun dispatchOpcode(opcode: Int) {
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protected open fun dispatchOpcode(opcode: Int): Boolean {
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when (opcode) {
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0x00 -> iBrk()
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0x01 -> iOra()
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@ -966,9 +982,9 @@ open class Cpu6502 : BusComponent() {
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0xfd -> iSbc()
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0xfe -> iInc()
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0xff -> iIsc()
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else -> { /* can't occur */
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}
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else -> { /* can't occur */ }
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}
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return false // TODO determine if instructions can cause extra clock cycle
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}
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@ -4,7 +4,6 @@ import razorvine.ksim65.components.Address
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/**
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* 65C02 cpu simulation (the CMOS version of the 6502).
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* TODO: add the optional additional cycles to certain instructions and addressing modes
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*/
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class Cpu65C02 : Cpu6502() {
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override val name = "65C02"
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@ -56,9 +55,10 @@ class Cpu65C02 : Cpu6502() {
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// branch-relative address fetched by the ZpR addressing mode
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private var fetchedAddressZpr: Address = 0
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override fun applyAddressingMode(addrMode: AddrMode) {
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when (addrMode) {
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AddrMode.Imp, AddrMode.Acc, AddrMode.Imm, AddrMode.Zp, AddrMode.ZpX, AddrMode.ZpY, AddrMode.Rel, AddrMode.Abs, AddrMode.AbsX, AddrMode.AbsY, AddrMode.IzX, AddrMode.IzY -> {
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override fun applyAddressingMode(addrMode: AddrMode): Boolean {
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return when (addrMode) {
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AddrMode.Imp, AddrMode.Acc, AddrMode.Imm, AddrMode.Zp, AddrMode.ZpX, AddrMode.ZpY,
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AddrMode.Rel, AddrMode.Abs, AddrMode.AbsX, AddrMode.AbsY, AddrMode.IzX, AddrMode.IzY -> {
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super.applyAddressingMode(addrMode)
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}
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AddrMode.Ind -> {
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@ -69,15 +69,16 @@ class Cpu65C02 : Cpu6502() {
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lo = read(fetchedAddress)
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hi = read(fetchedAddress+1)
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fetchedAddress = lo or (hi shl 8)
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false
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}
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AddrMode.Zpr -> {
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// addressing mode used by the 65C02 only
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// combination of zp addresssing + relative branch addressing
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// combination of zp addressing + relative branch addressing
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fetchedAddress = readPc()
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val relative = readPc()
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fetchedAddressZpr = if (relative >= 0x80) {
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regPC-(256-relative) and 0xffff
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} else regPC+relative and 0xffff
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fetchedAddressZpr =
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if (relative >= 0x80) regPC-(256-relative) and 0xffff else regPC+relative and 0xffff
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false
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}
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AddrMode.Izp -> {
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// addressing mode used by the 65C02 only
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@ -85,6 +86,7 @@ class Cpu65C02 : Cpu6502() {
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val lo = read((fetchedAddress) and 0xff)
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val hi = read((fetchedAddress+1) and 0xff)
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fetchedAddress = lo or (hi shl 8)
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false
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}
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AddrMode.IaX -> {
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// addressing mode used by the 65C02 only
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@ -94,11 +96,13 @@ class Cpu65C02 : Cpu6502() {
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lo = read((fetchedAddress+regX) and 0xffff)
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hi = read((fetchedAddress+regX+1) and 0xffff)
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fetchedAddress = lo or (hi shl 8)
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// if this address is a different page, extra clock cycle:
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(fetchedAddress and 0xff00) != hi shl 8
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}
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}
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}
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override fun dispatchOpcode(opcode: Int) {
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override fun dispatchOpcode(opcode: Int): Boolean {
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when (opcode) {
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0x00 -> iBrk()
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0x01 -> iOra()
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@ -356,9 +360,9 @@ class Cpu65C02 : Cpu6502() {
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0xfd -> iSbc()
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0xfe -> iInc()
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0xff -> iBbs7()
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else -> { /* can't occur */
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}
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else -> { /* can't occur */ }
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}
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return false // TODO determine if instructions can cause extra clock cycle
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}
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// opcode list: http://www.oxyron.de/html/opcodesc02.html
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