mirror of https://github.com/irmen/ksim65.git
67 lines
2.0 KiB
Kotlin
67 lines
2.0 KiB
Kotlin
package razorvine.ksim65.components
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import razorvine.ksim65.Bus
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typealias UByte = Short
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typealias Address = Int
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/**
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* Base class for any component connected to the system bus.
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*/
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abstract class BusComponent {
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lateinit var bus: Bus
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/**
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* One clock cycle on the bus
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*/
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abstract fun clock()
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/**
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* Reset all devices on the bus
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*/
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abstract fun reset()
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}
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/**
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* Base class for components that have registers mapped into the cpu's address space.
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* Most I/O components fall into this category.
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*/
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abstract class MemMappedComponent(val startAddress: Address, val endAddress: Address) : BusComponent() {
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abstract operator fun get(offset: Int): UByte
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abstract operator fun set(offset: Int, data: UByte)
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init {
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require(endAddress >= startAddress)
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require(startAddress >= 0 && endAddress <= 0xffff) { "can only have 16-bit address space" }
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}
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fun hexDump(from: Address, to: Address, charmapper: ((Short) -> Char)? = null) {
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(from..to).chunked(16).forEach {
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print("\$${it.first().toString(16).padStart(4, '0')} ")
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val bytes = it.map { address -> get(address - startAddress) }
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bytes.forEach { byte ->
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print(byte.toString(16).padStart(2, '0')+" ")
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}
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print(" ")
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val chars = if (charmapper != null) bytes.map { b -> charmapper(b) }
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else bytes.map { b -> if (b in 32..255) b.toInt().toChar() else '.' }
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println(chars.joinToString(""))
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}
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}
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}
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/**
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* Base class for components that actually contain memory (RAM or ROM chips).
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*/
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abstract class MemoryComponent(startAddress: Address, endAddress: Address) : MemMappedComponent(startAddress, endAddress) {
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abstract val data: Array<UByte>
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init {
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require(startAddress and 0xff == 0 && endAddress and 0xff == 0xff) { "address range must span complete page(s)" }
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}
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fun getBlock(start: Int, length: Int): Array<UByte> = data.copyOfRange(start, start+length)
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}
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