mirror of https://github.com/g012/l65.git
Added 0x64xx instructions.
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parent
a2e44ae24a
commit
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24
l7801.lua
24
l7801.lua
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@ -37,6 +37,7 @@ local Keywords_control = {
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local Keywords_data = {
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'dc',
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}
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local Keywords_7801 = {
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'aci','adi','adinc','ani','bit0','bit1','bit2','bit3',
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'bit4','bit5','bit6','bit7','block','calb','calf','call',
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@ -50,7 +51,7 @@ local Keywords_7801 = {
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'staw','stax','staxd','staxi','stc','stm','sui','suinb',
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'table','xri',
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'ana','xra','ora','addnc','gta','subnb','lta','add','adc','sub','nea','sbb','eqa',
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'ona','offa'
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'ona','offa',
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}
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local Registers_7801 = {
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a=8,b=8,c=8,d=8,e=8,h=8,l=8,v=8,
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@ -119,13 +120,14 @@ local opcode_timer = lookupify{
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}
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local opcode_reg_list = {
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a = lookupify{'aci','adi','adinc','ani','dcr','inr','eqi','gti','lti','mvi','nei','offi','oni','ori','rll','rlr','sbi','sll','slr','sui','suinb','xri'},
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b = lookupify{'dcr','inr','mvi'},
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c = lookupify{'dcr','inr','mvi','rll','rlr','sll','slr'},
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d = lookupify{'mvi'},
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e = lookupify{'mvi'},
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h = lookupify{'mvi'},
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l = lookupify{'mvi'},
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v = lookupify{'inrw','ldaw','dcrw','eqiw','mvi','mviw','staw',
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b = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi','dcr','inr','mvi'},
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c = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi','dcr','inr','mvi','rll','rlr','sll','slr'},
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d = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi','mvi'},
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e = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi','mvi'},
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h = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi','mvi'},
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l = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi','mvi'},
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v = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi',
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'inrw','ldaw','dcrw','eqiw','mvi','mviw','staw',
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'bit0','bit1','bit2','bit3','bit4','bit5','bit6','bit7',
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},
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bc = lookupify{'ldax','lxi','mvix','pop','push','stax'},
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@ -133,6 +135,10 @@ local opcode_reg_list = {
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hl = lookupify{'dcx','inx','ldax','ldaxd','ldaxi','lxi','mvix','pop','push','stax','staxd','staxi'},
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sp = lookupify{'dcx','inx','lxi'},
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va = lookupify{'pop','push'},
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pa = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi'},
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pb = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi'},
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pc = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi'},
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mk = lookupify{'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi'},
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}
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local opcode_reg_reg_list = {
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@ -1583,7 +1589,7 @@ local function ParseLua(src, src_name)
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if not Registers_7801[register_name] then
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return false, GenerateError(register_name .. " is not a valid register")
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end
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if not opcode_reg_list[register_name] and opcode_reg_list[register_name][op] then
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if (not opcode_reg_list[register_name]) and (not opcode_reg_list[register_name][op]) then
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return false, GenerateError("Opcode " .. op .. " doesn't support this addressing mode")
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end
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if opcode_regw[op] or opcode_regb[op] then
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@ -410,5 +410,185 @@ section{"rom", org=0x8000}
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eqa a,e
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eqa a,h
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eqa a,l
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ani v,0x00
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ani a,0x01
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ani b,0x02
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ani c,0x03
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ani d,0x04
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ani e,0x05
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ani h,0x06
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ani l,0x07
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xri v,0x08
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xri a,0x09
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xri b,0x0a
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xri c,0x0b
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xri d,0x0c
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xri e,0x0d
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xri h,0x0e
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xri l,0x0f
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ori v,0x10
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ori a,0x11
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ori b,0x12
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ori c,0x13
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ori d,0x14
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ori e,0x15
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ori h,0x16
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ori l,0x17
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adinc v,0x18
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adinc a,0x19
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adinc b,0x1a
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adinc c,0x1b
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adinc d,0x1c
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adinc e,0x1d
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adinc h,0x1e
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adinc l,0x1f
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gti v,0x20
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gti a,0x21
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gti b,0x22
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gti c,0x23
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gti d,0x24
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gti e,0x25
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gti h,0x26
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gti l,0x27
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suinb v,0x28
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suinb a,0x29
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suinb b,0x2a
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suinb c,0x2b
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suinb d,0x2c
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suinb e,0x2d
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suinb h,0x2e
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suinb l,0x2f
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lti v,0x30
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lti a,0x31
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lti b,0x32
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lti c,0x33
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lti d,0x34
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lti e,0x35
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lti h,0x36
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lti l,0x37
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adi v,0x38
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adi a,0x39
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adi b,0x3a
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adi c,0x3b
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adi d,0x3c
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adi e,0x3d
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adi h,0x3e
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adi l,0x4f
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oni v,0x40
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oni a,0x41
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oni b,0x42
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oni c,0x43
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oni d,0x44
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oni e,0x45
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oni h,0x46
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oni l,0x47
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aci v,0x48
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aci a,0x49
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aci b,0x4a
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aci c,0x4b
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aci d,0x4c
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aci e,0x4d
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aci h,0x4e
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aci l,0x4f
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offi v,0x50
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offi a,0x51
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offi b,0x52
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offi c,0x53
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offi d,0x54
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offi e,0x55
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offi h,0x56
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offi l,0x57
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sui v,0x58
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sui a,0x59
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sui b,0x5a
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sui c,0x5b
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sui d,0x5c
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sui e,0x5d
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sui h,0x5e
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sui l,0x5f
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nei v,0x60
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nei a,0x61
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nei b,0x62
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nei c,0x63
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nei d,0x64
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nei e,0x65
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nei h,0x66
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nei l,0x67
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sbi v,0x68
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sbi a,0x69
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sbi b,0x6a
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sbi c,0x6b
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sbi d,0x6c
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sbi e,0x6d
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sbi h,0x6e
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sbi l,0x6f
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eqi v,0x70
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eqi a,0x71
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eqi b,0x72
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eqi c,0x73
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eqi d,0x74
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eqi e,0x75
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eqi h,0x76
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eqi l,0x77
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ani pa,0x78
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ani pb,0x79
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ani pc,0x7a
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ani mk,0x7b
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xri pa,0x7c
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xri pb,0x7d
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xri pc,0x7e
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xri mk,0x7f
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ori pa,0x80
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ori pb,0x81
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ori pc,0x82
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ori mk,0x83
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adinc pa,0x84
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adinc pb,0x85
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adinc pc,0x86
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adinc mk,0x87
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gti pa,0x88
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gti pb,0x89
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gti pc,0x8a
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gti mk,0x8b
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suinb pa,0x8c
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suinb pb,0x8d
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suinb pc,0x8e
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suinb mk,0x8f
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lti pa,0x90
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lti pb,0x91
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lti pc,0x92
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lti mk,0x93
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adi pa,0x94
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adi pb,0x95
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adi pc,0x96
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adi mk,0x97
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oni pa,0x98
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oni pb,0x99
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oni pc,0x9a
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oni mk,0x9b
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aci pa,0x9c
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aci pb,0x9d
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aci pc,0x9e
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aci mk,0x9f
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offi pa,0xa0
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offi pb,0xa1
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offi pc,0xa2
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offi mk,0xa3
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sui pa,0xa4
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sui pb,0xa5
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sui pc,0xa6
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sui mk,0xa7
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nei pa,0xa8
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nei pb,0xa9
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nei pc,0xaa
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nei mk,0xab
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sbi pa,0xac
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sbi pb,0xad
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sbi pc,0xae
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sbi mk,0xaf
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eqi pa,0xb0
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eqi pb,0xb1
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eqi pc,0xb2
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eqi mk,0xb3
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writebin(filename .. '.bin')
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48
uPD7801.lua
48
uPD7801.lua
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@ -484,12 +484,58 @@ for i,o in ipairs(op60names) do
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end
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end
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k = 0x08
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local op64names = { 'ani','xri','ori','adinc','gti','suinb','lti','adi','oni','aci','offi','sui','nei','sbi','eqi' }
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for i,o in ipairs(op64names) do
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for j,r in ipairs(register_names) do
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local name = o .. r
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if not M[name] then
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local l = k
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M[name] = function(late,early)
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local l65dbg = { info=debug.getinfo(2, 'Sl'), trace=debug.traceback(nil, 1) }
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local op = { cycles=11 }
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op.size = function() late,early = M.size_op(late,early) return 3 end
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op.bin = function() local l65dbg=l65dbg
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local x = 0x00 + l;
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local y = 0x00 + M.op_eval_byte(late,early)
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return { 0x64, x, y }
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end
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table.insert(M.section_current.instructions, op)
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end
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end
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k = k + 1
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end
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end
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k = 0x88
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local ex_register_names = {'pa','pb','pc','mk'}
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for i,o in ipairs(op64names) do
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for j,r in ipairs(ex_register_names) do
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local name = o .. r
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if not M[name] then
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local l = k
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M[name] = function(late,early)
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local l65dbg = { info=debug.getinfo(2, 'Sl'), trace=debug.traceback(nil, 1) }
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local op = { cycles=11 }
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op.size = function() late,early = M.size_op(late,early) return 3 end
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op.bin = function() local l65dbg=l65dbg
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local x = 0x00 + l;
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local y = 0x00 + M.op_eval_byte(late,early)
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return { 0x64, x, y }
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end
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table.insert(M.section_current.instructions, op)
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end
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end
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k = k + 1
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end
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k = k + 4
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end
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return M
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--[[ [todo]
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16 bits instructions:
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0x64xx
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0x70xx
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0x74xx
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]]--
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