llvm-6502/test/CodeGen/PowerPC/varargs.ll

; RUN: llc < %s -mtriple=powerpc-apple-darwin | FileCheck -check-prefix=P32 %s
; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck -check-prefix=P64 %s

; PR8327
define i8* @test1(i8** %foo) nounwind {
  %A = va_arg i8** %foo, i8*
  ret i8* %A
}

; P32: test1:
; P32: 	lwz r4, 0(r3)
; P32:	addi r5, r4, 4
; P32:	stw r5, 0(r3)
; P32:	lwz r3, 0(r4)
; P32:	blr 

; P64: test1:
; P64: ld r4, 0(r3)
; P64: addi r5, r4, 8
; P64: std r5, 0(r3)
; P64: ld r3, 0(r4)
; P64: blr
force a triple, varargs isn't supported with the SVR4 ABI the buildbot tells me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116170 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-10 18:59:01 +00:00			`; RUN: llc < %s -mtriple=powerpc-apple-darwin \| FileCheck -check-prefix=P32 %s`
			`; RUN: llc < %s -mtriple=powerpc64-apple-darwin \| FileCheck -check-prefix=P64 %s`
fix the expansion of va_arg instruction on PPC to know the arg alignment for PPC32/64, avoiding some masking operations. llvm-gcc expands vaarg inline instead of using the instruction so it has never hit this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-10 18:34:00 +00:00
			`; PR8327`
			`define i8* @test1(i8** %foo) nounwind {`
			`%A = va_arg i8** %foo, i8*`
			`ret i8* %A`
			`}`

			`; P32: test1:`
			`; P32: lwz r4, 0(r3)`
			`; P32: addi r5, r4, 4`
			`; P32: stw r5, 0(r3)`
			`; P32: lwz r3, 0(r4)`
			`; P32: blr`

			`; P64: test1:`
			`; P64: ld r4, 0(r3)`
			`; P64: addi r5, r4, 8`
			`; P64: std r5, 0(r3)`
			`; P64: ld r3, 0(r4)`
			`; P64: blr`