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fix the expansion of va_arg instruction on PPC to know the arg

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alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-10-10 18:34:00 +00:00
parent 7d2e7bef90
commit 749dc72bdc
2 changed files with 26 additions and 0 deletions
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4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -73,6 +73,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setUseUnderscoreSetJmp(true);
setUseUnderscoreLongJmp(true);
// On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
// arguments are at least 4/8 bytes aligned.
setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
// Set up the register classes.
addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);

22
test/CodeGen/PowerPC/varargs.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc < %s -march=ppc32 | FileCheck -check-prefix=P32 %s
; RUN: llc < %s -march=ppc64 | FileCheck -check-prefix=P64 %s
; PR8327
define i8* @test1(i8** %foo) nounwind {
%A = va_arg i8** %foo, i8*
ret i8* %A
}
; P32: test1:
; P32: lwz r4, 0(r3)
; P32: addi r5, r4, 4
; P32: stw r5, 0(r3)
; P32: lwz r3, 0(r4)
; P32: blr
; P64: test1:
; P64: ld r4, 0(r3)
; P64: addi r5, r4, 8
; P64: std r5, 0(r3)
; P64: ld r3, 0(r4)
; P64: blr