llvm-6502/test/CodeGen/Mips/msa/elm_move.ll

; Test the MSA move intrinsics (which are encoded with the ELM instruction
; format).

; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s

@llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_move_vb_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

define void @llvm_mips_move_vb_test() nounwind {
entry:
  %0 = load <16 x i8>* @llvm_mips_move_vb_ARG1
  %1 = tail call <16 x i8> @llvm.mips.move.v(<16 x i8> %0)
  store <16 x i8> %1, <16 x i8>* @llvm_mips_move_vb_RES
  ret void
}

declare <16 x i8> @llvm.mips.move.v(<16 x i8>) nounwind

; CHECK: llvm_mips_move_vb_test:
; CHECK: ld.b
; CHECK: move.v
; CHECK: st.b
; CHECK: .size llvm_mips_move_vb_test
;
[mips][msa] Added move.v git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8 2013-08-28 10:44:47 +00:00			`; Test the MSA move intrinsics (which are encoded with the ELM instruction`
			`; format).`

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-27 10:08:31 +00:00			`; RUN: llc -march=mips -mattr=+msa,+fp64 < %s \| FileCheck %s`
[mips][msa] Build all the tests in little and big endian modes and correct an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws \| (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8 2013-11-15 11:04:16 +00:00			`; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s \| FileCheck %s`
[mips][msa] Added move.v git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8 2013-08-28 10:44:47 +00:00
			`@llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16`
			`@llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16`

			`define void @llvm_mips_move_vb_test() nounwind {`
			`entry:`
			`%0 = load <16 x i8>* @llvm_mips_move_vb_ARG1`
			`%1 = tail call <16 x i8> @llvm.mips.move.v(<16 x i8> %0)`
			`store <16 x i8> %1, <16 x i8>* @llvm_mips_move_vb_RES`
			`ret void`
			`}`

			`declare <16 x i8> @llvm.mips.move.v(<16 x i8>) nounwind`

			`; CHECK: llvm_mips_move_vb_test:`
			`; CHECK: ld.b`
			`; CHECK: move.v`
			`; CHECK: st.b`
			`; CHECK: .size llvm_mips_move_vb_test`
			`;`