2012-01-11 22:28:30 +00:00
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//===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RegAllocBase class which provides comon functionality
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// for LiveIntervalUnion-based register allocators.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RegAllocBase.h"
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2012-06-20 22:52:24 +00:00
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#include "LiveRegMatrix.h"
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2012-01-11 22:28:30 +00:00
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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2012-04-02 22:44:18 +00:00
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#include "llvm/CodeGen/LiveRangeEdit.h"
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2012-01-11 22:28:30 +00:00
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#ifndef NDEBUG
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#include "llvm/ADT/SparseBitVector.h"
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#endif
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Timer.h"
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using namespace llvm;
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STATISTIC(NumAssigned , "Number of registers assigned");
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STATISTIC(NumUnassigned , "Number of registers unassigned");
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STATISTIC(NumNewQueued , "Number of new live ranges queued");
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// Temporary verification option until we can put verification inside
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// MachineVerifier.
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static cl::opt<bool, true>
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VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
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cl::desc("Verify during register allocation"));
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const char *RegAllocBase::TimerGroupName = "Register Allocation";
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bool RegAllocBase::VerifyEnabled = false;
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#ifndef NDEBUG
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// Verify each LiveIntervalUnion.
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void RegAllocBase::verify() {
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LiveVirtRegBitSet VisitedVRegs;
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OwningArrayPtr<LiveVirtRegBitSet>
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2012-06-05 23:57:30 +00:00
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unionVRegs(new LiveVirtRegBitSet[TRI->getNumRegs()]);
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2012-01-11 22:28:30 +00:00
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// Verify disjoint unions.
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2012-06-05 23:57:30 +00:00
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for (unsigned PhysReg = 0, NumRegs = TRI->getNumRegs(); PhysReg != NumRegs;
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++PhysReg) {
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2012-01-11 22:28:30 +00:00
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DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
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LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
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PhysReg2LiveUnion[PhysReg].verify(VRegs);
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// Union + intersection test could be done efficiently in one pass, but
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// don't add a method to SparseBitVector unless we really need it.
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assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
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VisitedVRegs |= VRegs;
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}
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// Verify vreg coverage.
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2012-06-20 21:25:05 +00:00
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (MRI->reg_nodbg_empty(Reg))
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continue;
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if (!VRM->hasPhys(Reg)) continue; // spilled?
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LiveInterval &LI = LIS->getInterval(Reg);
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if (LI.empty()) continue; // unionVRegs will only be filled if li is
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// non-empty
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unsigned PhysReg = VRM->getPhys(Reg);
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if (!unionVRegs[PhysReg].test(Reg)) {
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dbgs() << "LiveVirtReg " << PrintReg(Reg, TRI) << " not in union "
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<< TRI->getName(PhysReg) << "\n";
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2012-01-11 22:28:30 +00:00
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llvm_unreachable("unallocated live vreg");
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}
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}
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// FIXME: I'm not sure how to verify spilled intervals.
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}
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#endif //!NDEBUG
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//===----------------------------------------------------------------------===//
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// RegAllocBase Implementation
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//===----------------------------------------------------------------------===//
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void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
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TRI = &vrm.getTargetRegInfo();
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MRI = &vrm.getRegInfo();
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VRM = &vrm;
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LIS = &lis;
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MRI->freezeReservedRegs(vrm.getMachineFunction());
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RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
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const unsigned NumRegs = TRI->getNumRegs();
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2012-06-05 23:57:30 +00:00
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if (NumRegs != PhysReg2LiveUnion.size()) {
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2012-01-11 22:28:30 +00:00
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PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
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// Cache an interferece query for each physical reg
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2012-06-05 23:57:30 +00:00
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Queries.reset(new LiveIntervalUnion::Query[NumRegs]);
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2012-01-11 22:28:30 +00:00
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}
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}
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void RegAllocBase::releaseMemory() {
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2012-06-05 23:57:30 +00:00
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for (unsigned r = 0, e = PhysReg2LiveUnion.size(); r != e; ++r)
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2012-01-11 22:28:30 +00:00
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PhysReg2LiveUnion[r].clear();
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}
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// Visit all the live registers. If they are already assigned to a physical
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// register, unify them with the corresponding LiveIntervalUnion, otherwise push
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// them on the priority queue for later assignment.
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void RegAllocBase::seedLiveRegs() {
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NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
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2012-06-20 21:25:05 +00:00
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// Physregs.
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for (unsigned Reg = 1, e = TRI->getNumRegs(); Reg != e; ++Reg) {
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if (!LIS->hasInterval(Reg))
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continue;
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PhysReg2LiveUnion[Reg].unify(LIS->getInterval(Reg));
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}
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// Virtregs.
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (MRI->reg_nodbg_empty(Reg))
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continue;
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enqueue(&LIS->getInterval(Reg));
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2012-01-11 22:28:30 +00:00
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}
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}
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void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
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2012-06-20 22:52:24 +00:00
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// FIXME: This diversion is temporary.
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if (Matrix) {
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Matrix->assign(VirtReg, PhysReg);
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return;
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}
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2012-01-11 22:28:30 +00:00
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DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
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<< " to " << PrintReg(PhysReg, TRI) << '\n');
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assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
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VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
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MRI->setPhysRegUsed(PhysReg);
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PhysReg2LiveUnion[PhysReg].unify(VirtReg);
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++NumAssigned;
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}
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void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
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2012-06-20 22:52:24 +00:00
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// FIXME: This diversion is temporary.
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if (Matrix) {
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Matrix->unassign(VirtReg);
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return;
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}
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2012-01-11 22:28:30 +00:00
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DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
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<< " from " << PrintReg(PhysReg, TRI) << '\n');
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assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
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PhysReg2LiveUnion[PhysReg].extract(VirtReg);
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VRM->clearVirt(VirtReg.reg);
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++NumUnassigned;
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}
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// Top-level driver to manage the queue of unassigned VirtRegs and call the
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// selectOrSplit implementation.
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void RegAllocBase::allocatePhysRegs() {
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seedLiveRegs();
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// Continue assigning vregs one at a time to available physical registers.
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while (LiveInterval *VirtReg = dequeue()) {
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assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
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// Unused registers can appear when the spiller coalesces snippets.
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if (MRI->reg_nodbg_empty(VirtReg->reg)) {
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DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
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LIS->removeInterval(VirtReg->reg);
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continue;
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}
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// Invalidate all interference queries, live ranges could have changed.
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invalidateVirtRegs();
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2012-06-20 22:52:24 +00:00
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if (Matrix)
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Matrix->invalidateVirtRegs();
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2012-01-11 22:28:30 +00:00
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// selectOrSplit requests the allocator to return an available physical
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// register if possible and populate a list of new live intervals that
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// result from splitting.
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DEBUG(dbgs() << "\nselectOrSplit "
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<< MRI->getRegClass(VirtReg->reg)->getName()
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2012-06-05 22:51:54 +00:00
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<< ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
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2012-01-11 22:28:30 +00:00
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typedef SmallVector<LiveInterval*, 4> VirtRegVec;
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VirtRegVec SplitVRegs;
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unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
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if (AvailablePhysReg == ~0u) {
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// selectOrSplit failed to find a register!
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const char *Msg = "ran out of registers during register allocation";
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// Probably caused by an inline asm.
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MachineInstr *MI;
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for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
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(MI = I.skipInstruction());)
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if (MI->isInlineAsm())
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break;
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if (MI)
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MI->emitError(Msg);
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else
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report_fatal_error(Msg);
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// Keep going after reporting the error.
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VRM->assignVirt2Phys(VirtReg->reg,
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RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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continue;
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}
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if (AvailablePhysReg)
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assign(*VirtReg, AvailablePhysReg);
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for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
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I != E; ++I) {
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LiveInterval *SplitVirtReg = *I;
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assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
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if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
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DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
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LIS->removeInterval(SplitVirtReg->reg);
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continue;
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}
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DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
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assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
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"expect split value in virtual register");
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enqueue(SplitVirtReg);
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++NumNewQueued;
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}
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}
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}
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// Check if this live virtual register interferes with a physical register. If
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// not, then check for interference on each register that aliases with the
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// physical register. Return the interfering register.
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unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
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unsigned PhysReg) {
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2012-06-01 23:28:30 +00:00
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for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
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if (query(VirtReg, *AI).checkInterference())
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return *AI;
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2012-01-11 22:28:30 +00:00
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return 0;
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}
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