llvm-6502/test/CodeGen/R600/store-v3i32.ll

; XFAIL: *
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s

; 3 vectors have the same size and alignment as 4 vectors, so this
; should be done in a single store.

; SI-LABEL: {{^}}store_v3i32:
; SI: BUFFER_STORE_DWORDX4
define void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind {
  store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16
  ret void
}
R600: Add failing testcase for <3 x i32> stores. This is supposed to have the same store size and alignment as <4 x i32>, but currently is split into a 64-bit and 32-bit store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204729 91177308-0d34-0410-b5e6-96231b3b80d8 2014-03-25 16:50:55 +00:00			`; XFAIL: *`
			`; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s \| FileCheck -check-prefix=SI %s`

			`; 3 vectors have the same size and alignment as 4 vectors, so this`
			`; should be done in a single store.`

R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218776 91177308-0d34-0410-b5e6-96231b3b80d8 2014-10-01 17:15:17 +00:00			`; SI-LABEL: {{^}}store_v3i32:`
R600: Add failing testcase for <3 x i32> stores. This is supposed to have the same store size and alignment as <4 x i32>, but currently is split into a 64-bit and 32-bit store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204729 91177308-0d34-0410-b5e6-96231b3b80d8 2014-03-25 16:50:55 +00:00			`; SI: BUFFER_STORE_DWORDX4`
			`define void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind {`
			`store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16`
			`ret void`
			`}`