Tom Stellard 1f06060994 R600/SI: Add an extra check line to make test more strict ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221349 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-05 14:50:34 +00:00
..
AArch64	[AArch64] Use the correct register class for ORR.	2014-11-04 22:20:07 +00:00
ARM	ARM: try to add extra CS-register whenever stack alignment >= 8.	2014-11-05 00:27:20 +00:00
CPP
Generic
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs
Mips	Revert "[mips] Add names and tests for the hardware registers"	2014-11-04 22:15:05 +00:00
MSP430
NVPTX	[NVPTX] aligned byte-buffers for vector return types	2014-10-25 03:46:16 +00:00
PowerPC	[PowerPC] Initial VSX intrinsic support, with min/max for vector double	2014-10-31 19:19:07 +00:00
R600	R600/SI: Add an extra check line to make test more strict	2014-11-05 14:50:34 +00:00
SPARC
SystemZ
Thumb	Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves.	2014-11-05 06:43:02 +00:00
Thumb2	ARM: Fix a bug which was causing convergence failure in constant-island pass.	2014-10-17 01:31:47 +00:00
X86	[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks.	2014-11-05 13:04:14 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00