llvm-6502/test/CodeGen/Hexagon/struct_args.ll

; RUN: true
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: r1:0 = or(r{{[0-9]}}:{{[0-9]}}, r{{[0-9]}}:{{[0-9]}})

%struct.small = type { i32, i32 }

@s1 = common global %struct.small zeroinitializer, align 4

define void @foo() nounwind {
entry:
  %0 = load i64* bitcast (%struct.small* @s1 to i64*), align 1
  call void @bar(i64 %0)
  ret void
}

declare void @bar(i64)
Disable Hexagon test temporarily. There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8 2012-04-12 21:06:54 +00:00			`; RUN: true`
			`; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s \| FileCheck %s`
Hexagon backend support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146412 91177308-0d34-0410-b5e6-96231b3b80d8 2011-12-12 21:14:40 +00:00			`; CHECK: r1:0 = or(r{{[0-9]}}:{{[0-9]}}, r{{[0-9]}}:{{[0-9]}})`

			`%struct.small = type { i32, i32 }`

			`@s1 = common global %struct.small zeroinitializer, align 4`

			`define void @foo() nounwind {`
			`entry:`
			`%0 = load i64* bitcast (%struct.small* @s1 to i64*), align 1`
			`call void @bar(i64 %0)`
			`ret void`
			`}`

			`declare void @bar(i64)`