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34 lines
1.4 KiB
TableGen
34 lines
1.4 KiB
TableGen
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//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM v7 processors.
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//
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//===----------------------------------------------------------------------===//
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def V7Itineraries : ProcessorItineraries<[
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InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>,
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InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>,
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InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>,
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InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>,
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InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>,
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>,
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InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]>
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]>;
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def CortexA8Itineraries : ProcessorItineraries<[
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InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>,
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InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>,
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InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>,
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InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>,
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InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>,
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>,
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InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]>
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]>;
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