2007-09-06 16:18:45 +00:00
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//===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-09-06 16:18:45 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the generic RegisterCoalescer interface which
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// is used as the common interface used by all clients and
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// implementations of register coalescing.
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//
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//===----------------------------------------------------------------------===//
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2012-01-07 07:39:47 +00:00
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#define DEBUG_TYPE "regalloc"
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2011-06-26 21:41:06 +00:00
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#include "RegisterCoalescer.h"
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2011-06-26 22:06:36 +00:00
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#include "LiveDebugVariables.h"
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2011-08-09 00:43:37 +00:00
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#include "RegisterClassInfo.h"
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#include "VirtRegMap.h"
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2011-06-26 22:06:36 +00:00
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#include "llvm/Pass.h"
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#include "llvm/Value.h"
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2012-05-19 05:25:50 +00:00
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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2007-09-06 16:18:45 +00:00
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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2011-06-26 22:06:36 +00:00
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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2012-05-19 05:25:50 +00:00
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#include "llvm/CodeGen/LiveRangeEdit.h"
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2011-06-26 22:06:36 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2012-05-19 05:25:50 +00:00
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#include "llvm/CodeGen/MachineInstr.h"
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2011-06-26 22:06:36 +00:00
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2012-05-19 05:25:50 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2011-06-26 22:06:36 +00:00
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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2012-05-19 05:25:50 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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2011-06-26 22:06:36 +00:00
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#include <algorithm>
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#include <cmath>
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2007-09-06 16:18:45 +00:00
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using namespace llvm;
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2011-06-26 22:06:36 +00:00
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STATISTIC(numJoins , "Number of interval joins performed");
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STATISTIC(numCrossRCs , "Number of cross class joins performed");
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STATISTIC(numCommutes , "Number of instruction commuting performed");
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STATISTIC(numExtends , "Number of copies extended");
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STATISTIC(NumReMats , "Number of instructions re-materialized");
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STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
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2011-08-09 18:19:41 +00:00
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STATISTIC(NumInflated , "Number of register classes inflated");
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2011-06-26 22:06:36 +00:00
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static cl::opt<bool>
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EnableJoining("join-liveintervals",
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cl::desc("Coalesce copies (default=true)"),
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cl::init(true));
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static cl::opt<bool>
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VerifyCoalescing("verify-coalescing",
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cl::desc("Verify machine instrs before and after register coalescing"),
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cl::Hidden);
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2011-08-09 00:43:37 +00:00
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namespace {
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2012-05-19 05:25:50 +00:00
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class RegisterCoalescer : public MachineFunctionPass,
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private LiveRangeEdit::Delegate {
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2011-08-09 01:01:27 +00:00
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MachineFunction* MF;
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MachineRegisterInfo* MRI;
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const TargetMachine* TM;
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const TargetRegisterInfo* TRI;
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const TargetInstrInfo* TII;
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LiveIntervals *LIS;
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LiveDebugVariables *LDV;
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const MachineLoopInfo* Loops;
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2011-08-09 00:43:37 +00:00
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AliasAnalysis *AA;
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RegisterClassInfo RegClassInfo;
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/// JoinedCopies - Keep track of copies eliminated due to coalescing.
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///
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SmallPtrSet<MachineInstr*, 32> JoinedCopies;
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/// ReMatDefs - Keep track of definition instructions which have
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/// been remat'ed.
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SmallPtrSet<MachineInstr*, 8> ReMatDefs;
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2012-05-18 21:09:40 +00:00
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/// WorkList - Copy instructions yet to be coalesced.
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SmallVector<MachineInstr*, 8> WorkList;
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2012-05-19 05:25:50 +00:00
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/// ErasedInstrs - Set of instruction pointers that have been erased, and
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/// that may be present in WorkList.
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SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
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/// Dead instructions that are about to be deleted.
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SmallVector<MachineInstr*, 8> DeadDefs;
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/// Recursively eliminate dead defs in DeadDefs.
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void eliminateDeadDefs();
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/// LiveRangeEdit callback.
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void LRE_WillEraseInstruction(MachineInstr *MI);
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2012-05-07 23:46:16 +00:00
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/// joinAllIntervals - join compatible live intervals
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void joinAllIntervals();
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2011-08-09 00:43:37 +00:00
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2012-05-07 23:46:16 +00:00
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/// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
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2012-05-18 21:09:40 +00:00
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/// copies that cannot yet be coalesced into WorkList.
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void copyCoalesceInMBB(MachineBasicBlock *MBB);
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/// copyCoalesceWorkList - Try to coalesce all copies in WorkList after
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/// position From. Return true if any progress was made.
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bool copyCoalesceWorkList(unsigned From = 0);
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2011-08-09 00:43:37 +00:00
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2012-05-07 23:46:16 +00:00
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/// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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2011-08-09 00:43:37 +00:00
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/// which are the src/dst of the copy instruction CopyMI. This returns
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/// true if the copy was successfully coalesced away. If it is not
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/// currently possible to coalesce this interval, but it may be possible if
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/// other things get coalesced, then it returns true by reference in
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/// 'Again'.
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2012-05-07 23:46:16 +00:00
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bool joinCopy(MachineInstr *TheCopy, bool &Again);
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2011-08-09 00:43:37 +00:00
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2012-05-07 23:46:16 +00:00
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/// joinIntervals - Attempt to join these two intervals. On failure, this
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2011-08-09 00:43:37 +00:00
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/// returns false. The output "SrcInt" will not have been modified, so we
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/// can use this information below to update aliases.
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2012-05-07 23:46:16 +00:00
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bool joinIntervals(CoalescerPair &CP);
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2011-08-09 00:43:37 +00:00
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2012-05-08 00:08:35 +00:00
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/// Attempt joining with a reserved physreg.
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bool joinReservedPhysReg(CoalescerPair &CP);
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2012-05-07 23:46:16 +00:00
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/// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
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2011-08-09 00:43:37 +00:00
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/// the source value number is defined by a copy from the destination reg
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/// see if we can merge these two destination reg valno# into a single
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/// value number, eliminating a copy.
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2012-05-07 23:46:16 +00:00
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bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
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2011-08-09 00:43:37 +00:00
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2012-05-07 23:46:16 +00:00
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/// hasOtherReachingDefs - Return true if there are definitions of IntB
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2011-08-09 00:43:37 +00:00
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/// other than BValNo val# that can reach uses of AValno val# of IntA.
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2012-05-07 23:46:16 +00:00
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bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
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2011-08-09 00:43:37 +00:00
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VNInfo *AValNo, VNInfo *BValNo);
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2012-05-07 23:46:16 +00:00
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/// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
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2011-08-09 00:43:37 +00:00
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/// If the source value number is defined by a commutable instruction and
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/// its other operand is coalesced to the copy dest register, see if we
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/// can transform the copy into a noop by commuting the definition.
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2012-05-07 23:46:16 +00:00
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bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
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2011-08-09 00:43:37 +00:00
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2012-05-07 23:46:16 +00:00
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/// reMaterializeTrivialDef - If the source of a copy is defined by a
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2011-08-09 00:43:37 +00:00
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/// trivial computation, replace the copy by rematerialize the definition.
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/// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
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2012-05-07 23:46:16 +00:00
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bool reMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
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2011-10-05 21:22:53 +00:00
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unsigned DstReg, MachineInstr *CopyMI);
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2011-08-09 00:43:37 +00:00
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2012-05-18 17:18:58 +00:00
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/// canJoinPhys - Return true if a physreg copy should be joined.
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bool canJoinPhys(CoalescerPair &CP);
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2011-08-09 00:43:37 +00:00
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2012-05-07 23:46:16 +00:00
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/// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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2011-08-09 00:43:37 +00:00
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/// update the subregister number if it is not zero. If DstReg is a
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/// physical register and the existing subregister number of the def / use
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/// being updated is not zero, make sure to set it to the correct physical
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/// subregister.
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2012-05-15 22:26:28 +00:00
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void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
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2011-08-09 00:43:37 +00:00
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2012-05-07 23:46:16 +00:00
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/// removeDeadDef - If a def of a live interval is now determined dead,
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2011-08-09 00:43:37 +00:00
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/// remove the val# it defines. If the live interval becomes empty, remove
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/// it as well.
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2012-05-07 23:46:16 +00:00
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bool removeDeadDef(LiveInterval &li, MachineInstr *DefMI);
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2011-08-09 00:43:37 +00:00
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/// markAsJoined - Remember that CopyMI has already been joined.
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void markAsJoined(MachineInstr *CopyMI);
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/// eliminateUndefCopy - Handle copies of undef values.
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bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
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public:
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static char ID; // Class identification, replacement for typeinfo
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RegisterCoalescer() : MachineFunctionPass(ID) {
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initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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};
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} /// end anonymous namespace
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2012-02-10 04:10:36 +00:00
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char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
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2011-08-09 00:29:53 +00:00
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2011-06-26 22:34:10 +00:00
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INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
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"Simple Register Coalescing", false, false)
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2011-06-26 22:06:36 +00:00
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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2011-06-26 22:34:10 +00:00
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INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
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"Simple Register Coalescing", false, false)
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2011-06-26 22:06:36 +00:00
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2007-09-06 16:18:45 +00:00
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char RegisterCoalescer::ID = 0;
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2011-06-29 20:55:48 +00:00
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static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
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2010-06-15 16:04:21 +00:00
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if (!a) return b;
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if (!b) return a;
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2011-06-29 20:55:48 +00:00
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return tri.composeSubRegIndices(a, b);
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2010-06-15 16:04:21 +00:00
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}
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2011-06-29 20:55:48 +00:00
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static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
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unsigned &Src, unsigned &Dst,
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unsigned &SrcSub, unsigned &DstSub) {
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2010-07-03 00:04:37 +00:00
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if (MI->isCopy()) {
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Dst = MI->getOperand(0).getReg();
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DstSub = MI->getOperand(0).getSubReg();
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Src = MI->getOperand(1).getReg();
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SrcSub = MI->getOperand(1).getSubReg();
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2010-07-08 16:40:15 +00:00
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} else if (MI->isSubregToReg()) {
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2010-06-15 16:04:21 +00:00
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Dst = MI->getOperand(0).getReg();
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2011-06-29 20:55:48 +00:00
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DstSub = compose(tri, MI->getOperand(0).getSubReg(),
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MI->getOperand(3).getImm());
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2010-06-15 16:04:21 +00:00
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Src = MI->getOperand(2).getReg();
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SrcSub = MI->getOperand(2).getSubReg();
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2010-07-16 04:45:42 +00:00
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} else
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2010-06-15 16:04:21 +00:00
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return false;
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return true;
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}
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bool CoalescerPair::setRegisters(const MachineInstr *MI) {
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2012-05-15 20:09:43 +00:00
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SrcReg = DstReg = 0;
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SrcIdx = DstIdx = 0;
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2011-08-09 01:01:27 +00:00
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NewRC = 0;
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Flipped = CrossClass = false;
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2010-06-15 16:04:21 +00:00
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unsigned Src, Dst, SrcSub, DstSub;
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2011-08-09 01:01:27 +00:00
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if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
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2010-06-15 16:04:21 +00:00
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return false;
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2011-08-09 01:01:27 +00:00
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Partial = SrcSub || DstSub;
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2010-06-15 16:04:21 +00:00
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// If one register is a physreg, it must be Dst.
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if (TargetRegisterInfo::isPhysicalRegister(Src)) {
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if (TargetRegisterInfo::isPhysicalRegister(Dst))
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return false;
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std::swap(Src, Dst);
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std::swap(SrcSub, DstSub);
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2011-08-09 01:01:27 +00:00
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Flipped = true;
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2010-06-15 16:04:21 +00:00
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}
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const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
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// Eliminate DstSub on a physreg.
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if (DstSub) {
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2011-08-09 01:01:27 +00:00
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Dst = TRI.getSubReg(Dst, DstSub);
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2010-06-15 16:04:21 +00:00
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if (!Dst) return false;
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DstSub = 0;
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}
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// Eliminate SrcSub by picking a corresponding Dst superregister.
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if (SrcSub) {
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2011-08-09 01:01:27 +00:00
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Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
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2010-06-15 16:04:21 +00:00
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if (!Dst) return false;
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SrcSub = 0;
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} else if (!MRI.getRegClass(Src)->contains(Dst)) {
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return false;
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}
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} else {
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// Both registers are virtual.
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2012-05-07 22:57:55 +00:00
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const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
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const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
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2010-06-15 16:04:21 +00:00
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2010-06-24 16:19:28 +00:00
|
|
|
// Both registers have subreg indices.
|
|
|
|
if (SrcSub && DstSub) {
|
2012-05-15 22:26:28 +00:00
|
|
|
// Copies between different sub-registers are never coalescable.
|
|
|
|
if (Src == Dst && SrcSub != DstSub)
|
|
|
|
return false;
|
|
|
|
|
2012-05-07 22:57:55 +00:00
|
|
|
NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
|
2012-05-15 20:09:43 +00:00
|
|
|
SrcIdx, DstIdx);
|
2012-05-07 22:57:55 +00:00
|
|
|
if (!NewRC)
|
2010-06-24 16:19:28 +00:00
|
|
|
return false;
|
2012-05-15 20:09:43 +00:00
|
|
|
} else if (DstSub) {
|
|
|
|
// SrcReg will be merged with a sub-register of DstReg.
|
|
|
|
SrcIdx = DstSub;
|
|
|
|
NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
|
|
|
|
} else if (SrcSub) {
|
|
|
|
// DstReg will be merged with a sub-register of SrcReg.
|
|
|
|
DstIdx = SrcSub;
|
|
|
|
NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
|
|
|
|
} else {
|
|
|
|
// This is a straight copy without sub-registers.
|
|
|
|
NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
|
2010-06-24 16:19:28 +00:00
|
|
|
}
|
2010-06-15 16:04:21 +00:00
|
|
|
|
2012-05-15 20:09:43 +00:00
|
|
|
// The combined constraint may be impossible to satisfy.
|
|
|
|
if (!NewRC)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Prefer SrcReg to be a sub-register of DstReg.
|
|
|
|
// FIXME: Coalescer should support subregs symmetrically.
|
|
|
|
if (DstIdx && !SrcIdx) {
|
2010-06-15 16:04:21 +00:00
|
|
|
std::swap(Src, Dst);
|
2012-05-15 20:09:43 +00:00
|
|
|
std::swap(SrcIdx, DstIdx);
|
|
|
|
Flipped = !Flipped;
|
2010-06-15 16:04:21 +00:00
|
|
|
}
|
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
CrossClass = NewRC != DstRC || NewRC != SrcRC;
|
2010-06-15 16:04:21 +00:00
|
|
|
}
|
|
|
|
// Check our invariants
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
|
|
|
|
assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
|
|
|
|
"Cannot have a physical SubIdx");
|
2011-08-09 01:01:27 +00:00
|
|
|
SrcReg = Src;
|
|
|
|
DstReg = Dst;
|
2010-06-15 16:04:21 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool CoalescerPair::flip() {
|
2012-05-15 20:09:43 +00:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(DstReg))
|
2010-06-15 16:04:21 +00:00
|
|
|
return false;
|
2011-08-09 01:01:27 +00:00
|
|
|
std::swap(SrcReg, DstReg);
|
2012-05-15 20:09:43 +00:00
|
|
|
std::swap(SrcIdx, DstIdx);
|
2011-08-09 01:01:27 +00:00
|
|
|
Flipped = !Flipped;
|
2010-06-15 16:04:21 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
|
|
|
|
if (!MI)
|
|
|
|
return false;
|
|
|
|
unsigned Src, Dst, SrcSub, DstSub;
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
|
2010-06-15 16:04:21 +00:00
|
|
|
return false;
|
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
// Find the virtual register that is SrcReg.
|
|
|
|
if (Dst == SrcReg) {
|
2010-06-15 16:04:21 +00:00
|
|
|
std::swap(Src, Dst);
|
|
|
|
std::swap(SrcSub, DstSub);
|
2011-08-09 01:01:27 +00:00
|
|
|
} else if (Src != SrcReg) {
|
2010-06-15 16:04:21 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
// Now check that Dst matches DstReg.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
|
2010-06-15 16:04:21 +00:00
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(Dst))
|
|
|
|
return false;
|
2012-05-15 20:09:43 +00:00
|
|
|
assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
|
2010-06-15 16:04:21 +00:00
|
|
|
// DstSub could be set for a physreg from INSERT_SUBREG.
|
|
|
|
if (DstSub)
|
2011-08-09 01:01:27 +00:00
|
|
|
Dst = TRI.getSubReg(Dst, DstSub);
|
2010-06-15 16:04:21 +00:00
|
|
|
// Full copy of Src.
|
|
|
|
if (!SrcSub)
|
2011-08-09 01:01:27 +00:00
|
|
|
return DstReg == Dst;
|
2010-06-15 16:04:21 +00:00
|
|
|
// This is a partial register copy. Check that the parts match.
|
2011-08-09 01:01:27 +00:00
|
|
|
return TRI.getSubReg(DstReg, SrcSub) == Dst;
|
2010-06-15 16:04:21 +00:00
|
|
|
} else {
|
2011-08-09 01:01:27 +00:00
|
|
|
// DstReg is virtual.
|
|
|
|
if (DstReg != Dst)
|
2010-06-15 16:04:21 +00:00
|
|
|
return false;
|
|
|
|
// Registers match, do the subregisters line up?
|
2012-05-15 20:09:43 +00:00
|
|
|
return compose(TRI, SrcIdx, SrcSub) == compose(TRI, DstIdx, DstSub);
|
2010-06-15 16:04:21 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:34:10 +00:00
|
|
|
void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
|
2011-06-26 22:06:36 +00:00
|
|
|
AU.setPreservesCFG();
|
|
|
|
AU.addRequired<AliasAnalysis>();
|
|
|
|
AU.addRequired<LiveIntervals>();
|
|
|
|
AU.addPreserved<LiveIntervals>();
|
|
|
|
AU.addRequired<LiveDebugVariables>();
|
|
|
|
AU.addPreserved<LiveDebugVariables>();
|
|
|
|
AU.addPreserved<SlotIndexes>();
|
|
|
|
AU.addRequired<MachineLoopInfo>();
|
|
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
|
|
AU.addPreservedID(MachineDominatorsID);
|
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:34:10 +00:00
|
|
|
void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) {
|
2011-06-26 22:06:36 +00:00
|
|
|
/// Joined copies are not deleted immediately, but kept in JoinedCopies.
|
|
|
|
JoinedCopies.insert(CopyMI);
|
|
|
|
|
|
|
|
/// Mark all register operands of CopyMI as <undef> so they won't affect dead
|
|
|
|
/// code elimination.
|
|
|
|
for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
|
|
|
|
E = CopyMI->operands_end(); I != E; ++I)
|
|
|
|
if (I->isReg())
|
|
|
|
I->setIsUndef(true);
|
|
|
|
}
|
|
|
|
|
2012-05-19 05:25:50 +00:00
|
|
|
void RegisterCoalescer::eliminateDeadDefs() {
|
|
|
|
SmallVector<LiveInterval*, 8> NewRegs;
|
|
|
|
LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Callback from eliminateDeadDefs().
|
|
|
|
void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
|
|
|
|
// MI may be in WorkList. Make sure we don't visit it.
|
|
|
|
ErasedInstrs.insert(MI);
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
|
2011-06-26 22:06:36 +00:00
|
|
|
/// being the source and IntB being the dest, thus this defines a value number
|
|
|
|
/// in IntB. If the source value number (in IntA) is defined by a copy from B,
|
|
|
|
/// see if we can merge these two pieces of B into a single value number,
|
|
|
|
/// eliminating a copy. For example:
|
|
|
|
///
|
|
|
|
/// A3 = B0
|
|
|
|
/// ...
|
|
|
|
/// B1 = A3 <- this copy
|
|
|
|
///
|
|
|
|
/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
|
|
|
|
/// value number to be replaced with B0 (which simplifies the B liveinterval).
|
|
|
|
///
|
|
|
|
/// This returns true if an interval was modified.
|
|
|
|
///
|
2012-05-07 23:46:16 +00:00
|
|
|
bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
|
|
|
|
MachineInstr *CopyMI) {
|
2012-05-15 22:18:49 +00:00
|
|
|
assert(!CP.isPartial() && "This doesn't work for partial copies.");
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// Bail if there is no dst interval - can happen when merging physical subreg
|
|
|
|
// operations.
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!LIS->hasInterval(CP.getDstReg()))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
LiveInterval &IntA =
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval &IntB =
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
// BValNo is a value number in B that is defined by a copy from A. 'B3' in
|
|
|
|
// the example above.
|
|
|
|
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
|
|
|
|
if (BLR == IntB.end()) return false;
|
|
|
|
VNInfo *BValNo = BLR->valno;
|
|
|
|
|
|
|
|
// Get the location that B is defined at. Two options: either this value has
|
|
|
|
// an unknown definition point or it is defined at CopyIdx. If unknown, we
|
|
|
|
// can't process it.
|
2012-02-04 05:20:49 +00:00
|
|
|
if (BValNo->def != CopyIdx) return false;
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
// AValNo is the value number in A that defines the copy, A3 in the example.
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
|
|
|
|
// The live range might not exist after fun with physreg coalescing.
|
|
|
|
if (ALR == IntA.end()) return false;
|
|
|
|
VNInfo *AValNo = ALR->valno;
|
|
|
|
|
|
|
|
// If AValNo is defined as a copy from IntB, we can potentially process this.
|
|
|
|
// Get the instruction that defines this value number.
|
2012-02-04 05:20:49 +00:00
|
|
|
MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
|
|
|
|
if (!CP.isCoalescable(ACopyMI))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Get the LiveRange in IntB that this value number starts with.
|
|
|
|
LiveInterval::iterator ValLR =
|
|
|
|
IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
|
|
|
|
if (ValLR == IntB.end())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Make sure that the end of the live range is inside the same block as
|
|
|
|
// CopyMI.
|
|
|
|
MachineInstr *ValLREndInst =
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
|
2011-06-26 22:06:36 +00:00
|
|
|
if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Okay, we now know that ValLR ends in the same block that the CopyMI
|
|
|
|
// live-range starts. If there are no intervening live ranges between them in
|
|
|
|
// IntB, we can merge them.
|
|
|
|
if (ValLR+1 != BLR) return false;
|
|
|
|
|
|
|
|
// If a live interval is a physical register, conservatively check if any
|
|
|
|
// of its aliases is overlapping the live interval of the virtual register.
|
|
|
|
// If so, do not coalesce.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
|
2012-03-04 10:43:23 +00:00
|
|
|
for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
|
2011-08-09 01:01:27 +00:00
|
|
|
if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
|
2011-06-26 22:06:36 +00:00
|
|
|
DEBUG({
|
|
|
|
dbgs() << "\t\tInterfere with alias ";
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getInterval(*AS).print(dbgs(), TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
});
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << "Extending: ";
|
2011-08-09 01:01:27 +00:00
|
|
|
IntB.print(dbgs(), TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
});
|
|
|
|
|
|
|
|
SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
|
|
|
|
// We are about to delete CopyMI, so need to remove it as the 'instruction
|
|
|
|
// that defines this value #'. Update the valnum with the new defining
|
|
|
|
// instruction #.
|
2012-02-04 05:20:49 +00:00
|
|
|
BValNo->def = FillerStart;
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
// Okay, we can merge them. We need to insert a new liverange:
|
|
|
|
// [ValLR.end, BLR.begin) of either value number, then we merge the
|
|
|
|
// two value numbers.
|
|
|
|
IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
|
|
|
|
|
|
|
|
// If the IntB live range is assigned to a physical register, and if that
|
|
|
|
// physreg has sub-registers, update their live intervals as well.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
|
2012-03-05 05:37:41 +00:00
|
|
|
for (const uint16_t *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!LIS->hasInterval(*SR))
|
2011-06-26 22:06:36 +00:00
|
|
|
continue;
|
2011-08-09 01:01:27 +00:00
|
|
|
LiveInterval &SRLI = LIS->getInterval(*SR);
|
2011-06-26 22:06:36 +00:00
|
|
|
SRLI.addRange(LiveRange(FillerStart, FillerEnd,
|
2012-02-04 05:20:49 +00:00
|
|
|
SRLI.getNextValue(FillerStart,
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getVNInfoAllocator())));
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Okay, merge "B1" into the same value number as "B0".
|
|
|
|
if (BValNo != ValLR->valno) {
|
|
|
|
// If B1 is killed by a PHI, then the merged live range must also be killed
|
|
|
|
// by the same PHI, as B0 and B1 can not overlap.
|
|
|
|
bool HasPHIKill = BValNo->hasPHIKill();
|
|
|
|
IntB.MergeValueNumberInto(BValNo, ValLR->valno);
|
|
|
|
if (HasPHIKill)
|
|
|
|
ValLR->valno->setHasPHIKill(true);
|
|
|
|
}
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << " result = ";
|
2011-08-09 01:01:27 +00:00
|
|
|
IntB.print(dbgs(), TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
dbgs() << "\n";
|
|
|
|
});
|
|
|
|
|
|
|
|
// If the source instruction was killing the source register before the
|
|
|
|
// merge, unset the isKill marker given the live range has been extended.
|
|
|
|
int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
|
|
|
|
if (UIdx != -1) {
|
|
|
|
ValLREndInst->getOperand(UIdx).setIsKill(false);
|
|
|
|
}
|
2012-02-10 04:10:36 +00:00
|
|
|
|
2012-01-27 00:05:42 +00:00
|
|
|
// Rewrite the copy. If the copy instruction was killing the destination
|
|
|
|
// register before the merge, find the last use and trim the live range. That
|
|
|
|
// will also add the isKill marker.
|
2012-05-15 22:18:49 +00:00
|
|
|
CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
if (ALR->end == CopyIdx)
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->shrinkToUses(&IntA);
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
++numExtends;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// hasOtherReachingDefs - Return true if there are definitions of IntB
|
2011-09-15 06:27:32 +00:00
|
|
|
/// other than BValNo val# that can reach uses of AValno val# of IntA.
|
2012-05-07 23:46:16 +00:00
|
|
|
bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
|
|
|
|
LiveInterval &IntB,
|
|
|
|
VNInfo *AValNo,
|
|
|
|
VNInfo *BValNo) {
|
2011-06-26 22:06:36 +00:00
|
|
|
for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
|
|
|
|
AI != AE; ++AI) {
|
2011-09-15 06:27:32 +00:00
|
|
|
if (AI->valno != AValNo) continue;
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval::Ranges::iterator BI =
|
|
|
|
std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
|
|
|
|
if (BI != IntB.ranges.begin())
|
|
|
|
--BI;
|
|
|
|
for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
|
|
|
|
if (BI->valno == BValNo)
|
|
|
|
continue;
|
|
|
|
if (BI->start <= AI->start && BI->end > AI->start)
|
|
|
|
return true;
|
|
|
|
if (BI->start > AI->start && BI->start < AI->end)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
|
2011-06-26 22:06:36 +00:00
|
|
|
/// IntA being the source and IntB being the dest, thus this defines a value
|
|
|
|
/// number in IntB. If the source value number (in IntA) is defined by a
|
|
|
|
/// commutable instruction and its other operand is coalesced to the copy dest
|
|
|
|
/// register, see if we can transform the copy into a noop by commuting the
|
|
|
|
/// definition. For example,
|
|
|
|
///
|
|
|
|
/// A3 = op A2 B0<kill>
|
|
|
|
/// ...
|
|
|
|
/// B1 = A3 <- this copy
|
|
|
|
/// ...
|
|
|
|
/// = op A3 <- more uses
|
|
|
|
///
|
|
|
|
/// ==>
|
|
|
|
///
|
|
|
|
/// B2 = op B0 A2<kill>
|
|
|
|
/// ...
|
|
|
|
/// B1 = B2 <- now an identify copy
|
|
|
|
/// ...
|
|
|
|
/// = op B2 <- more uses
|
|
|
|
///
|
|
|
|
/// This returns true if an interval was modified.
|
|
|
|
///
|
2012-05-07 23:46:16 +00:00
|
|
|
bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
|
|
|
|
MachineInstr *CopyMI) {
|
2011-06-26 22:06:36 +00:00
|
|
|
// FIXME: For now, only eliminate the copy by commuting its def when the
|
|
|
|
// source register is a virtual register. We want to guard against cases
|
|
|
|
// where the copy is a back edge copy and commuting the def lengthen the
|
|
|
|
// live interval of the source register to the entire loop.
|
|
|
|
if (CP.isPhys() && CP.isFlipped())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Bail if there is no dst interval.
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!LIS->hasInterval(CP.getDstReg()))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
LiveInterval &IntA =
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval &IntB =
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
// BValNo is a value number in B that is defined by a copy from A. 'B3' in
|
|
|
|
// the example above.
|
|
|
|
VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
|
2012-02-04 05:20:49 +00:00
|
|
|
if (!BValNo || BValNo->def != CopyIdx)
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
|
|
|
|
|
|
|
|
// AValNo is the value number in A that defines the copy, A3 in the example.
|
2011-11-13 20:45:27 +00:00
|
|
|
VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
|
2011-06-26 22:06:36 +00:00
|
|
|
assert(AValNo && "COPY source not live");
|
|
|
|
|
2011-09-15 06:27:32 +00:00
|
|
|
// If other defs can reach uses of this def, then it's not safe to perform
|
|
|
|
// the optimization.
|
|
|
|
if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
2011-08-09 01:01:27 +00:00
|
|
|
MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
|
2011-06-26 22:06:36 +00:00
|
|
|
if (!DefMI)
|
|
|
|
return false;
|
2011-12-07 07:15:52 +00:00
|
|
|
if (!DefMI->isCommutable())
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
// If DefMI is a two-address instruction then commuting it will change the
|
|
|
|
// destination register.
|
|
|
|
int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
|
|
|
|
assert(DefIdx != -1);
|
|
|
|
unsigned UseOpIdx;
|
|
|
|
if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
|
|
|
|
return false;
|
|
|
|
unsigned Op1, Op2, NewDstIdx;
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
if (Op1 == UseOpIdx)
|
|
|
|
NewDstIdx = Op2;
|
|
|
|
else if (Op2 == UseOpIdx)
|
|
|
|
NewDstIdx = Op1;
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
|
|
|
|
unsigned NewReg = NewDstMO.getReg();
|
|
|
|
if (NewReg != IntB.reg || !NewDstMO.isKill())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Make sure there are no other definitions of IntB that would reach the
|
|
|
|
// uses which the new definition can reach.
|
2012-05-07 23:46:16 +00:00
|
|
|
if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Abort if the aliases of IntB.reg have values that are not simply the
|
|
|
|
// clobbers from the superreg.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
|
2012-03-04 10:43:23 +00:00
|
|
|
for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
|
2011-08-09 01:01:27 +00:00
|
|
|
if (LIS->hasInterval(*AS) &&
|
2012-05-07 23:46:16 +00:00
|
|
|
hasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// If some of the uses of IntA.reg is already coalesced away, return false.
|
|
|
|
// It's not possible to determine whether it's safe to perform the coalescing.
|
2011-09-15 01:09:33 +00:00
|
|
|
for (MachineRegisterInfo::use_nodbg_iterator UI =
|
2011-08-09 01:01:27 +00:00
|
|
|
MRI->use_nodbg_begin(IntA.reg),
|
|
|
|
UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
|
2011-06-26 22:06:36 +00:00
|
|
|
MachineInstr *UseMI = &*UI;
|
2011-08-09 01:01:27 +00:00
|
|
|
SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
|
|
|
|
if (ULR == IntA.end())
|
|
|
|
continue;
|
|
|
|
if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
|
2011-06-26 22:06:36 +00:00
|
|
|
<< *DefMI);
|
|
|
|
|
|
|
|
// At this point we have decided that it is legal to do this
|
|
|
|
// transformation. Start by commuting the instruction.
|
|
|
|
MachineBasicBlock *MBB = DefMI->getParent();
|
2011-08-09 01:01:27 +00:00
|
|
|
MachineInstr *NewMI = TII->commuteInstruction(DefMI);
|
2011-06-26 22:06:36 +00:00
|
|
|
if (!NewMI)
|
|
|
|
return false;
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
|
|
|
|
TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
|
2011-08-09 01:01:27 +00:00
|
|
|
!MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
if (NewMI != DefMI) {
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
|
2011-12-06 22:12:01 +00:00
|
|
|
MachineBasicBlock::iterator Pos = DefMI;
|
|
|
|
MBB->insert(Pos, NewMI);
|
2011-06-26 22:06:36 +00:00
|
|
|
MBB->erase(DefMI);
|
|
|
|
}
|
|
|
|
unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
|
|
|
|
NewMI->getOperand(OpIdx).setIsKill();
|
|
|
|
|
|
|
|
// If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
|
|
|
|
// A = or A, B
|
|
|
|
// ...
|
|
|
|
// B = A
|
|
|
|
// ...
|
|
|
|
// C = A<kill>
|
|
|
|
// ...
|
|
|
|
// = B
|
|
|
|
|
|
|
|
// Update uses of IntA of the specific Val# with IntB.
|
2011-08-09 01:01:27 +00:00
|
|
|
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
|
|
|
|
UE = MRI->use_end(); UI != UE;) {
|
2011-06-26 22:06:36 +00:00
|
|
|
MachineOperand &UseMO = UI.getOperand();
|
|
|
|
MachineInstr *UseMI = &*UI;
|
|
|
|
++UI;
|
|
|
|
if (JoinedCopies.count(UseMI))
|
|
|
|
continue;
|
|
|
|
if (UseMI->isDebugValue()) {
|
|
|
|
// FIXME These don't have an instruction index. Not clear we have enough
|
|
|
|
// info to decide whether to do this replacement or not. For now do it.
|
|
|
|
UseMO.setReg(NewReg);
|
|
|
|
continue;
|
|
|
|
}
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
|
|
|
|
if (ULR == IntA.end() || ULR->valno != AValNo)
|
|
|
|
continue;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(NewReg))
|
2011-08-09 01:01:27 +00:00
|
|
|
UseMO.substPhysReg(NewReg, *TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
else
|
|
|
|
UseMO.setReg(NewReg);
|
|
|
|
if (UseMI == CopyMI)
|
|
|
|
continue;
|
|
|
|
if (!UseMI->isCopy())
|
|
|
|
continue;
|
|
|
|
if (UseMI->getOperand(0).getReg() != IntB.reg ||
|
|
|
|
UseMI->getOperand(0).getSubReg())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// This copy will become a noop. If it's defining a new val#, merge it into
|
|
|
|
// BValNo.
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex DefIdx = UseIdx.getRegSlot();
|
2011-06-26 22:06:36 +00:00
|
|
|
VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
|
|
|
|
if (!DVNI)
|
|
|
|
continue;
|
|
|
|
DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
|
|
|
|
assert(DVNI->def == DefIdx);
|
|
|
|
BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
|
|
|
|
markAsJoined(UseMI);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
|
|
|
|
// is updated.
|
|
|
|
VNInfo *ValNo = BValNo;
|
|
|
|
ValNo->def = AValNo->def;
|
|
|
|
for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
|
|
|
|
AI != AE; ++AI) {
|
|
|
|
if (AI->valno != AValNo) continue;
|
|
|
|
IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
|
|
|
|
}
|
|
|
|
DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
|
|
|
|
|
|
|
|
IntA.removeValNo(AValNo);
|
|
|
|
DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
|
|
|
|
++numCommutes;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
|
2011-06-26 22:06:36 +00:00
|
|
|
/// computation, replace the copy by rematerialize the definition.
|
2012-05-07 23:46:16 +00:00
|
|
|
bool RegisterCoalescer::reMaterializeTrivialDef(LiveInterval &SrcInt,
|
|
|
|
bool preserveSrcInt,
|
|
|
|
unsigned DstReg,
|
|
|
|
MachineInstr *CopyMI) {
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
|
|
|
|
assert(SrcLR != SrcInt.end() && "Live range not found!");
|
|
|
|
VNInfo *ValNo = SrcLR->valno;
|
2011-09-15 04:52:06 +00:00
|
|
|
if (ValNo->isPHIDef() || ValNo->isUnused())
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
2011-08-09 01:01:27 +00:00
|
|
|
MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
|
2011-06-26 22:06:36 +00:00
|
|
|
if (!DefMI)
|
|
|
|
return false;
|
|
|
|
assert(DefMI && "Defining instruction disappeared");
|
2011-12-07 07:15:52 +00:00
|
|
|
if (!DefMI->isAsCheapAsAMove())
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!TII->isTriviallyReMaterializable(DefMI, AA))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
bool SawStore = false;
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!DefMI->isSafeToMove(TII, AA, SawStore))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
2011-12-07 07:15:52 +00:00
|
|
|
const MCInstrDesc &MCID = DefMI->getDesc();
|
2011-06-28 19:10:37 +00:00
|
|
|
if (MCID.getNumDefs() != 1)
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
if (!DefMI->isImplicitDef()) {
|
|
|
|
// Make sure the copy destination register class fits the instruction
|
|
|
|
// definition register class. The mismatch can happen as a result of earlier
|
|
|
|
// extract_subreg, insert_subreg, subreg_to_reg coalescing.
|
2012-05-07 22:10:26 +00:00
|
|
|
const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
|
2011-06-26 22:06:36 +00:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
|
2011-08-09 01:01:27 +00:00
|
|
|
if (MRI->getRegClass(DstReg) != RC)
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
} else if (!RC->contains(DstReg))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *MBB = CopyMI->getParent();
|
|
|
|
MachineBasicBlock::iterator MII =
|
|
|
|
llvm::next(MachineBasicBlock::iterator(CopyMI));
|
2011-10-05 21:22:53 +00:00
|
|
|
TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
MachineInstr *NewMI = prior(MII);
|
|
|
|
|
2012-02-02 08:01:53 +00:00
|
|
|
// NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
|
|
|
|
// We need to remember these so we can add intervals once we insert
|
|
|
|
// NewMI into SlotIndexes.
|
|
|
|
SmallVector<unsigned, 4> NewMIImplDefs;
|
|
|
|
for (unsigned i = NewMI->getDesc().getNumOperands(),
|
|
|
|
e = NewMI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = NewMI->getOperand(i);
|
|
|
|
if (MO.isReg()) {
|
2012-03-01 00:41:17 +00:00
|
|
|
assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
|
|
|
|
TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
|
2012-02-02 08:01:53 +00:00
|
|
|
NewMIImplDefs.push_back(MO.getReg());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// CopyMI may have implicit operands, transfer them over to the newly
|
|
|
|
// rematerialized instruction. And update implicit def interval valnos.
|
|
|
|
for (unsigned i = CopyMI->getDesc().getNumOperands(),
|
|
|
|
e = CopyMI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = CopyMI->getOperand(i);
|
2012-03-01 00:41:17 +00:00
|
|
|
if (MO.isReg()) {
|
|
|
|
assert(MO.isImplicit() && "No explicit operands after implict operands.");
|
|
|
|
// Discard VReg implicit defs.
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
|
|
|
|
NewMI->addOperand(MO);
|
|
|
|
}
|
|
|
|
}
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
|
2012-02-02 08:01:53 +00:00
|
|
|
|
|
|
|
SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
|
|
|
|
for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
|
|
|
|
unsigned reg = NewMIImplDefs[i];
|
|
|
|
LiveInterval &li = LIS->getInterval(reg);
|
2012-02-04 05:20:49 +00:00
|
|
|
VNInfo *DeadDefVN = li.getNextValue(NewMIIdx.getRegSlot(),
|
2012-02-02 08:01:53 +00:00
|
|
|
LIS->getVNInfoAllocator());
|
|
|
|
LiveRange lr(NewMIIdx.getRegSlot(), NewMIIdx.getDeadSlot(), DeadDefVN);
|
|
|
|
li.addRange(lr);
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
CopyMI->eraseFromParent();
|
2012-05-19 05:25:50 +00:00
|
|
|
ErasedInstrs.insert(CopyMI);
|
2011-06-26 22:06:36 +00:00
|
|
|
ReMatDefs.insert(DefMI);
|
|
|
|
DEBUG(dbgs() << "Remat: " << *NewMI);
|
|
|
|
++NumReMats;
|
|
|
|
|
|
|
|
// The source interval can become smaller because we removed a use.
|
|
|
|
if (preserveSrcInt)
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->shrinkToUses(&SrcInt);
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-07-26 23:00:24 +00:00
|
|
|
/// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
|
|
|
|
/// values, it only removes local variables. When we have a copy like:
|
|
|
|
///
|
|
|
|
/// %vreg1 = COPY %vreg2<undef>
|
|
|
|
///
|
|
|
|
/// We delete the copy and remove the corresponding value number from %vreg1.
|
|
|
|
/// Any uses of that value number are marked as <undef>.
|
|
|
|
bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
|
|
|
|
const CoalescerPair &CP) {
|
2011-08-09 01:01:27 +00:00
|
|
|
SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
|
|
|
|
LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
|
2011-07-26 23:00:24 +00:00
|
|
|
if (SrcInt->liveAt(Idx))
|
|
|
|
return false;
|
2011-08-09 01:01:27 +00:00
|
|
|
LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
|
2011-07-26 23:00:24 +00:00
|
|
|
if (DstInt->liveAt(Idx))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// No intervals are live-in to CopyMI - it is undef.
|
|
|
|
if (CP.isFlipped())
|
|
|
|
DstInt = SrcInt;
|
|
|
|
SrcInt = 0;
|
|
|
|
|
2011-11-13 20:45:27 +00:00
|
|
|
VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
|
2011-07-26 23:00:24 +00:00
|
|
|
assert(DeadVNI && "No value defined in DstInt");
|
|
|
|
DstInt->removeValNo(DeadVNI);
|
|
|
|
|
|
|
|
// Find new undef uses.
|
|
|
|
for (MachineRegisterInfo::reg_nodbg_iterator
|
2011-08-09 01:01:27 +00:00
|
|
|
I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
|
2011-07-26 23:00:24 +00:00
|
|
|
I != E; ++I) {
|
|
|
|
MachineOperand &MO = I.getOperand();
|
|
|
|
if (MO.isDef() || MO.isUndef())
|
|
|
|
continue;
|
|
|
|
MachineInstr *MI = MO.getParent();
|
2011-08-09 01:01:27 +00:00
|
|
|
SlotIndex Idx = LIS->getInstructionIndex(MI);
|
2011-07-26 23:00:24 +00:00
|
|
|
if (DstInt->liveAt(Idx))
|
|
|
|
continue;
|
|
|
|
MO.setIsUndef(true);
|
|
|
|
DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
|
2011-06-26 22:06:36 +00:00
|
|
|
/// update the subregister number if it is not zero. If DstReg is a
|
|
|
|
/// physical register and the existing subregister number of the def / use
|
|
|
|
/// being updated is not zero, make sure to set it to the correct physical
|
|
|
|
/// subregister.
|
2012-05-15 22:26:28 +00:00
|
|
|
void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
|
|
|
|
unsigned DstReg,
|
|
|
|
unsigned SubIdx) {
|
|
|
|
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
|
2012-05-16 21:22:35 +00:00
|
|
|
LiveInterval &DstInt = LIS->getInterval(DstReg);
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
// Update LiveDebugVariables.
|
2011-08-09 01:01:27 +00:00
|
|
|
LDV->renameRegister(SrcReg, DstReg, SubIdx);
|
2011-06-26 22:06:36 +00:00
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
|
2011-06-26 22:06:36 +00:00
|
|
|
MachineInstr *UseMI = I.skipInstruction();) {
|
2012-05-17 18:32:42 +00:00
|
|
|
bool AlreadyJoined = JoinedCopies.count(UseMI);
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// A PhysReg copy that won't be coalesced can perhaps be rematerialized
|
|
|
|
// instead.
|
|
|
|
if (DstIsPhys) {
|
2011-09-02 18:18:29 +00:00
|
|
|
if (UseMI->isFullCopy() &&
|
2011-06-26 22:06:36 +00:00
|
|
|
UseMI->getOperand(1).getReg() == SrcReg &&
|
|
|
|
UseMI->getOperand(0).getReg() != SrcReg &&
|
|
|
|
UseMI->getOperand(0).getReg() != DstReg &&
|
2012-05-17 18:32:42 +00:00
|
|
|
!AlreadyJoined &&
|
2012-05-07 23:46:16 +00:00
|
|
|
reMaterializeTrivialDef(LIS->getInterval(SrcReg), false,
|
2011-10-05 21:22:53 +00:00
|
|
|
UseMI->getOperand(0).getReg(), UseMI))
|
2011-06-26 22:06:36 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
SmallVector<unsigned,8> Ops;
|
|
|
|
bool Reads, Writes;
|
|
|
|
tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
|
|
|
|
|
2012-05-16 21:22:35 +00:00
|
|
|
// If SrcReg wasn't read, it may still be the case that DstReg is live-in
|
|
|
|
// because SrcReg is a sub-register.
|
2012-05-17 18:32:42 +00:00
|
|
|
if (!Reads && SubIdx && !AlreadyJoined)
|
2012-05-16 21:22:35 +00:00
|
|
|
Reads = DstInt.liveAt(LIS->getInstructionIndex(UseMI));
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// Replace SrcReg with DstReg in all UseMI operands.
|
|
|
|
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = UseMI->getOperand(Ops[i]);
|
|
|
|
|
2012-05-16 21:22:35 +00:00
|
|
|
// Adjust <undef> flags in case of sub-register joins. We don't want to
|
|
|
|
// turn a full def into a read-modify-write sub-register def and vice
|
|
|
|
// versa.
|
2012-05-17 18:32:42 +00:00
|
|
|
if (SubIdx && !AlreadyJoined && MO.isDef())
|
2012-05-16 21:22:35 +00:00
|
|
|
MO.setIsUndef(!Reads);
|
2011-10-05 00:01:46 +00:00
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
if (DstIsPhys)
|
2011-08-09 01:01:27 +00:00
|
|
|
MO.substPhysReg(DstReg, *TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
else
|
2011-08-09 01:01:27 +00:00
|
|
|
MO.substVirtReg(DstReg, SubIdx, *TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// This instruction is a copy that will be removed.
|
2012-05-17 18:32:42 +00:00
|
|
|
if (AlreadyJoined)
|
2011-06-26 22:06:36 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
DEBUG({
|
|
|
|
dbgs() << "\t\tupdated: ";
|
|
|
|
if (!UseMI->isDebugValue())
|
2011-08-09 01:01:27 +00:00
|
|
|
dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
|
2011-06-26 22:06:36 +00:00
|
|
|
dbgs() << *UseMI;
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// removeIntervalIfEmpty - Check if the live interval of a physical register
|
|
|
|
/// is empty, if so remove it and also remove the empty intervals of its
|
|
|
|
/// sub-registers. Return true if live interval is removed.
|
2011-08-09 01:01:27 +00:00
|
|
|
static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
|
|
|
|
const TargetRegisterInfo *TRI) {
|
2011-06-26 22:06:36 +00:00
|
|
|
if (li.empty()) {
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(li.reg))
|
2012-03-05 05:37:41 +00:00
|
|
|
for (const uint16_t* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!LIS->hasInterval(*SR))
|
2011-06-26 22:06:36 +00:00
|
|
|
continue;
|
2011-08-09 01:01:27 +00:00
|
|
|
LiveInterval &sli = LIS->getInterval(*SR);
|
2011-06-26 22:06:36 +00:00
|
|
|
if (sli.empty())
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->removeInterval(*SR);
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->removeInterval(li.reg);
|
2011-06-26 22:06:36 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// removeDeadDef - If a def of a live interval is now determined dead, remove
|
2011-06-26 22:06:36 +00:00
|
|
|
/// the val# it defines. If the live interval becomes empty, remove it as well.
|
2012-05-07 23:46:16 +00:00
|
|
|
bool RegisterCoalescer::removeDeadDef(LiveInterval &li, MachineInstr *DefMI) {
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
|
2011-06-26 22:06:36 +00:00
|
|
|
LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
|
|
|
|
if (DefIdx != MLR->valno->def)
|
|
|
|
return false;
|
|
|
|
li.removeValNo(MLR->valno);
|
2011-08-09 01:01:27 +00:00
|
|
|
return removeIntervalIfEmpty(li, LIS, TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
2012-05-18 17:18:58 +00:00
|
|
|
/// canJoinPhys - Return true if a copy involving a physreg should be joined.
|
|
|
|
bool RegisterCoalescer::canJoinPhys(CoalescerPair &CP) {
|
2011-06-26 22:06:36 +00:00
|
|
|
/// Always join simple intervals that are defined by a single copy from a
|
|
|
|
/// reserved register. This doesn't increase register pressure, so it is
|
|
|
|
/// always beneficial.
|
2012-05-18 17:18:58 +00:00
|
|
|
if (!RegClassInfo.isReserved(CP.getDstReg())) {
|
|
|
|
DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
|
2011-06-26 22:06:36 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-05-18 17:18:58 +00:00
|
|
|
LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
|
|
|
|
if (CP.isFlipped() && JoinVInt.containsOneValue())
|
|
|
|
return true;
|
2011-06-26 22:06:36 +00:00
|
|
|
|
2012-05-18 17:18:58 +00:00
|
|
|
DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
|
|
|
|
return false;
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
|
2011-06-26 22:06:36 +00:00
|
|
|
/// which are the src/dst of the copy instruction CopyMI. This returns true
|
|
|
|
/// if the copy was successfully coalesced away. If it is not currently
|
|
|
|
/// possible to coalesce this interval, but it may be possible if other
|
|
|
|
/// things get coalesced, then it returns true by reference in 'Again'.
|
2012-05-07 23:46:16 +00:00
|
|
|
bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
Again = false;
|
2012-05-19 05:25:50 +00:00
|
|
|
if (JoinedCopies.count(CopyMI))
|
2011-06-26 22:06:36 +00:00
|
|
|
return false; // Already done.
|
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
|
2011-06-26 22:06:36 +00:00
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
CoalescerPair CP(*TII, *TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
if (!CP.setRegisters(CopyMI)) {
|
|
|
|
DEBUG(dbgs() << "\tNot coalescable.\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-05-19 05:25:50 +00:00
|
|
|
// Dead code elimination. This really should be handled by MachineDCE, but
|
|
|
|
// sometimes dead copies slip through, and we can't generate invalid live
|
|
|
|
// ranges.
|
|
|
|
if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
|
|
|
|
DEBUG(dbgs() << "\tCopy is dead.\n");
|
|
|
|
DeadDefs.push_back(CopyMI);
|
|
|
|
eliminateDeadDefs();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// If they are already joined we continue.
|
|
|
|
if (CP.getSrcReg() == CP.getDstReg()) {
|
|
|
|
DEBUG(dbgs() << "\tCopy already coalesced.\n");
|
2012-05-19 05:25:53 +00:00
|
|
|
LIS->RemoveMachineInstrFromMaps(CopyMI);
|
|
|
|
CopyMI->eraseFromParent();
|
2011-06-26 22:06:36 +00:00
|
|
|
return false; // Not coalescable.
|
|
|
|
}
|
|
|
|
|
2011-07-26 23:00:24 +00:00
|
|
|
// Eliminate undefs.
|
|
|
|
if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
|
|
|
|
DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
|
2012-05-19 05:25:53 +00:00
|
|
|
LIS->RemoveMachineInstrFromMaps(CopyMI);
|
|
|
|
CopyMI->eraseFromParent();
|
2011-07-26 23:00:24 +00:00
|
|
|
return false; // Not coalescable.
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// Enforce policies.
|
|
|
|
if (CP.isPhys()) {
|
2012-05-15 22:26:28 +00:00
|
|
|
DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
|
|
|
|
<< " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
|
|
|
|
<< '\n');
|
2012-05-18 17:18:58 +00:00
|
|
|
if (!canJoinPhys(CP)) {
|
2011-06-26 22:06:36 +00:00
|
|
|
// Before giving up coalescing, if definition of source is defined by
|
|
|
|
// trivial computation, try rematerializing it.
|
|
|
|
if (!CP.isFlipped() &&
|
2012-05-07 23:46:16 +00:00
|
|
|
reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
|
2011-10-05 21:22:53 +00:00
|
|
|
CP.getDstReg(), CopyMI))
|
2011-06-26 22:06:36 +00:00
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
} else {
|
2012-04-25 16:17:50 +00:00
|
|
|
DEBUG({
|
2012-05-15 22:26:28 +00:00
|
|
|
dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
|
|
|
|
<< " with ";
|
|
|
|
if (CP.getDstIdx() && CP.getSrcIdx())
|
|
|
|
dbgs() << PrintReg(CP.getDstReg()) << " in "
|
|
|
|
<< TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
|
|
|
|
<< PrintReg(CP.getSrcReg()) << " in "
|
|
|
|
<< TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
|
|
|
|
else
|
|
|
|
dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
|
|
|
|
<< PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
|
2012-04-25 16:17:50 +00:00
|
|
|
});
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
// When possible, let DstReg be the larger interval.
|
2012-05-15 22:26:28 +00:00
|
|
|
if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->getInterval(CP.getDstReg()).ranges.size())
|
2011-06-26 22:06:36 +00:00
|
|
|
CP.flip();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Okay, attempt to join these two intervals. On failure, this returns false.
|
|
|
|
// Otherwise, if one of the intervals being joined is a physreg, this method
|
|
|
|
// always canonicalizes DstInt to be it. The output "SrcInt" will not have
|
|
|
|
// been modified, so we can use this information below to update aliases.
|
2012-05-07 23:46:16 +00:00
|
|
|
if (!joinIntervals(CP)) {
|
2011-06-26 22:06:36 +00:00
|
|
|
// Coalescing failed.
|
|
|
|
|
|
|
|
// If definition of source is defined by trivial computation, try
|
|
|
|
// rematerializing it.
|
|
|
|
if (!CP.isFlipped() &&
|
2012-05-07 23:46:16 +00:00
|
|
|
reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
|
2011-10-05 21:22:53 +00:00
|
|
|
CP.getDstReg(), CopyMI))
|
2011-06-26 22:06:36 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
// If we can eliminate the copy without merging the live ranges, do so now.
|
|
|
|
if (!CP.isPartial()) {
|
2012-05-07 23:46:16 +00:00
|
|
|
if (adjustCopiesBackFrom(CP, CopyMI) ||
|
|
|
|
removeCopyByCommutingDef(CP, CopyMI)) {
|
2011-06-26 22:06:36 +00:00
|
|
|
markAsJoined(CopyMI);
|
|
|
|
DEBUG(dbgs() << "\tTrivial!\n");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Otherwise, we are unable to join the intervals.
|
|
|
|
DEBUG(dbgs() << "\tInterference!\n");
|
|
|
|
Again = true; // May be possible to coalesce later.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Coalescing to a virtual register that is of a sub-register class of the
|
|
|
|
// other. Make sure the resulting register is set to the right register class.
|
|
|
|
if (CP.isCrossClass()) {
|
|
|
|
++numCrossRCs;
|
2011-08-09 01:01:27 +00:00
|
|
|
MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Remember to delete the copy instruction.
|
|
|
|
markAsJoined(CopyMI);
|
|
|
|
|
2012-05-15 22:26:28 +00:00
|
|
|
// Rewrite all SrcReg operands to DstReg.
|
|
|
|
// Also update DstReg operands to include DstIdx if it is set.
|
|
|
|
if (CP.getDstIdx())
|
|
|
|
updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
|
|
|
|
updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
|
2011-06-26 22:06:36 +00:00
|
|
|
|
2012-01-17 00:39:29 +00:00
|
|
|
// SrcReg is guaranteed to be the register whose live interval that is
|
2011-06-26 22:06:36 +00:00
|
|
|
// being merged.
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->removeInterval(CP.getSrcReg());
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
// Update regalloc hint.
|
2011-08-09 01:01:27 +00:00
|
|
|
TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
DEBUG({
|
2011-08-09 01:01:27 +00:00
|
|
|
LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
|
2011-06-26 22:06:36 +00:00
|
|
|
dbgs() << "\tJoined. Result = ";
|
2011-08-09 01:01:27 +00:00
|
|
|
DstInt.print(dbgs(), TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
dbgs() << "\n";
|
|
|
|
});
|
|
|
|
|
|
|
|
++numJoins;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-05-08 00:08:35 +00:00
|
|
|
/// Attempt joining with a reserved physreg.
|
|
|
|
bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
|
|
|
|
assert(CP.isPhys() && "Must be a physreg copy");
|
|
|
|
assert(RegClassInfo.isReserved(CP.getDstReg()) && "Not a reserved register");
|
|
|
|
LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
|
|
|
|
DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
|
|
|
|
|
|
|
|
assert(CP.isFlipped() && RHS.containsOneValue() &&
|
|
|
|
"Invalid join with reserved register");
|
|
|
|
|
|
|
|
// Optimization for reserved registers like ESP. We can only merge with a
|
|
|
|
// reserved physreg if RHS has a single value that is a copy of CP.DstReg().
|
|
|
|
// The live range of the reserved register will look like a set of dead defs
|
|
|
|
// - we don't properly track the live range of reserved registers.
|
|
|
|
|
|
|
|
// Deny any overlapping intervals. This depends on all the reserved
|
|
|
|
// register live ranges to look like dead defs.
|
|
|
|
for (const uint16_t *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
|
|
|
|
if (!LIS->hasInterval(*AS)) {
|
|
|
|
// Make sure at least DstReg itself exists before attempting a join.
|
|
|
|
if (*AS == CP.getDstReg())
|
|
|
|
LIS->getOrCreateInterval(CP.getDstReg());
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (RHS.overlaps(LIS->getInterval(*AS))) {
|
|
|
|
DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Skip any value computations, we are not adding new values to the
|
|
|
|
// reserved register. Also skip merging the live ranges, the reserved
|
|
|
|
// register live range doesn't need to be accurate as long as all the
|
|
|
|
// defs are there.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
/// ComputeUltimateVN - Assuming we are going to join two live intervals,
|
|
|
|
/// compute what the resultant value numbers for each value in the input two
|
|
|
|
/// ranges will be. This is complicated by copies between the two which can
|
|
|
|
/// and will commonly cause multiple value numbers to be merged into one.
|
|
|
|
///
|
|
|
|
/// VN is the value number that we're trying to resolve. InstDefiningValue
|
|
|
|
/// keeps track of the new InstDefiningValue assignment for the result
|
|
|
|
/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
|
|
|
|
/// whether a value in this or other is a copy from the opposite set.
|
|
|
|
/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
|
|
|
|
/// already been assigned.
|
|
|
|
///
|
|
|
|
/// ThisFromOther[x] - If x is defined as a copy from the other interval, this
|
|
|
|
/// contains the value number the copy is from.
|
|
|
|
///
|
|
|
|
static unsigned ComputeUltimateVN(VNInfo *VNI,
|
|
|
|
SmallVector<VNInfo*, 16> &NewVNInfo,
|
|
|
|
DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
|
|
|
|
DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
|
|
|
|
SmallVector<int, 16> &ThisValNoAssignments,
|
|
|
|
SmallVector<int, 16> &OtherValNoAssignments) {
|
|
|
|
unsigned VN = VNI->id;
|
|
|
|
|
|
|
|
// If the VN has already been computed, just return it.
|
|
|
|
if (ThisValNoAssignments[VN] >= 0)
|
|
|
|
return ThisValNoAssignments[VN];
|
|
|
|
assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
|
|
|
|
|
|
|
|
// If this val is not a copy from the other val, then it must be a new value
|
|
|
|
// number in the destination.
|
|
|
|
DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
|
|
|
|
if (I == ThisFromOther.end()) {
|
|
|
|
NewVNInfo.push_back(VNI);
|
|
|
|
return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
|
|
|
|
}
|
|
|
|
VNInfo *OtherValNo = I->second;
|
|
|
|
|
|
|
|
// Otherwise, this *is* a copy from the RHS. If the other side has already
|
|
|
|
// been computed, return it.
|
|
|
|
if (OtherValNoAssignments[OtherValNo->id] >= 0)
|
|
|
|
return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
|
|
|
|
|
|
|
|
// Mark this value number as currently being computed, then ask what the
|
|
|
|
// ultimate value # of the other value is.
|
|
|
|
ThisValNoAssignments[VN] = -2;
|
|
|
|
unsigned UltimateVN =
|
|
|
|
ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
|
|
|
|
OtherValNoAssignments, ThisValNoAssignments);
|
|
|
|
return ThisValNoAssignments[VN] = UltimateVN;
|
|
|
|
}
|
|
|
|
|
2011-07-01 00:16:54 +00:00
|
|
|
|
|
|
|
// Find out if we have something like
|
|
|
|
// A = X
|
|
|
|
// B = X
|
|
|
|
// if so, we can pretend this is actually
|
|
|
|
// A = X
|
|
|
|
// B = A
|
|
|
|
// which allows us to coalesce A and B.
|
2011-07-01 04:15:02 +00:00
|
|
|
// VNI is the definition of B. LR is the life range of A that includes
|
2011-07-01 00:16:54 +00:00
|
|
|
// the slot just before B. If we return true, we add "B = X" to DupCopies.
|
2011-09-15 01:09:33 +00:00
|
|
|
// This implies that A dominates B.
|
2011-07-01 02:35:06 +00:00
|
|
|
static bool RegistersDefinedFromSameValue(LiveIntervals &li,
|
|
|
|
const TargetRegisterInfo &tri,
|
2011-07-01 04:15:02 +00:00
|
|
|
CoalescerPair &CP,
|
|
|
|
VNInfo *VNI,
|
2011-07-01 00:16:54 +00:00
|
|
|
LiveRange *LR,
|
|
|
|
SmallVector<MachineInstr*, 8> &DupCopies) {
|
|
|
|
// FIXME: This is very conservative. For example, we don't handle
|
|
|
|
// physical registers.
|
|
|
|
|
2012-02-04 05:20:49 +00:00
|
|
|
MachineInstr *MI = li.getInstructionFromIndex(VNI->def);
|
2011-07-01 04:15:02 +00:00
|
|
|
|
2012-02-04 05:20:49 +00:00
|
|
|
if (!MI || !MI->isFullCopy() || CP.isPartial() || CP.isPhys())
|
2011-07-01 00:16:54 +00:00
|
|
|
return false;
|
|
|
|
|
2011-07-01 02:35:06 +00:00
|
|
|
unsigned Dst = MI->getOperand(0).getReg();
|
|
|
|
unsigned Src = MI->getOperand(1).getReg();
|
|
|
|
|
2011-07-01 00:16:54 +00:00
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(Src) ||
|
|
|
|
!TargetRegisterInfo::isVirtualRegister(Dst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned A = CP.getDstReg();
|
|
|
|
unsigned B = CP.getSrcReg();
|
|
|
|
|
|
|
|
if (B == Dst)
|
|
|
|
std::swap(A, B);
|
|
|
|
assert(Dst == A);
|
|
|
|
|
|
|
|
VNInfo *Other = LR->valno;
|
2012-02-04 05:20:49 +00:00
|
|
|
const MachineInstr *OtherMI = li.getInstructionFromIndex(Other->def);
|
2011-07-01 00:16:54 +00:00
|
|
|
|
2012-02-04 05:20:49 +00:00
|
|
|
if (!OtherMI || !OtherMI->isFullCopy())
|
2011-07-01 00:16:54 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned OtherDst = OtherMI->getOperand(0).getReg();
|
|
|
|
unsigned OtherSrc = OtherMI->getOperand(1).getReg();
|
|
|
|
|
|
|
|
if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
|
|
|
|
!TargetRegisterInfo::isVirtualRegister(OtherDst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
assert(OtherDst == B);
|
|
|
|
|
|
|
|
if (Src != OtherSrc)
|
|
|
|
return false;
|
|
|
|
|
2011-07-02 05:34:02 +00:00
|
|
|
// If the copies use two different value numbers of X, we cannot merge
|
|
|
|
// A and B.
|
2011-07-03 05:26:42 +00:00
|
|
|
LiveInterval &SrcInt = li.getInterval(Src);
|
2011-09-15 01:09:33 +00:00
|
|
|
// getVNInfoBefore returns NULL for undef copies. In this case, the
|
|
|
|
// optimization is still safe.
|
|
|
|
if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
|
2011-07-02 05:34:02 +00:00
|
|
|
return false;
|
|
|
|
|
2011-07-01 00:16:54 +00:00
|
|
|
DupCopies.push_back(MI);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
/// joinIntervals - Attempt to join these two intervals. On failure, this
|
2011-06-26 22:06:36 +00:00
|
|
|
/// returns false.
|
2012-05-07 23:46:16 +00:00
|
|
|
bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
|
2012-05-08 00:08:35 +00:00
|
|
|
// Handle physreg joins separately.
|
2012-05-18 17:18:58 +00:00
|
|
|
if (CP.isPhys())
|
|
|
|
return joinReservedPhysReg(CP);
|
2011-06-26 22:06:36 +00:00
|
|
|
|
2012-05-08 00:08:35 +00:00
|
|
|
LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
|
|
|
|
DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// Compute the final value assignment, assuming that the live ranges can be
|
|
|
|
// coalesced.
|
|
|
|
SmallVector<int, 16> LHSValNoAssignments;
|
|
|
|
SmallVector<int, 16> RHSValNoAssignments;
|
|
|
|
DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
|
|
|
|
DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
|
|
|
|
SmallVector<VNInfo*, 16> NewVNInfo;
|
|
|
|
|
2011-07-01 00:16:54 +00:00
|
|
|
SmallVector<MachineInstr*, 8> DupCopies;
|
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
|
|
|
|
DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
|
2011-06-26 22:06:36 +00:00
|
|
|
|
2012-01-27 21:43:32 +00:00
|
|
|
// Loop over the value numbers of the LHS, seeing if any are defined from
|
|
|
|
// the RHS.
|
|
|
|
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
|
|
|
|
i != e; ++i) {
|
|
|
|
VNInfo *VNI = *i;
|
2012-02-04 05:20:49 +00:00
|
|
|
if (VNI->isUnused() || VNI->isPHIDef())
|
|
|
|
continue;
|
|
|
|
MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
|
|
|
|
assert(MI && "Missing def");
|
|
|
|
if (!MI->isCopyLike()) // Src not defined by a copy?
|
2012-01-27 21:43:32 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Figure out the value # from the RHS.
|
|
|
|
LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
|
|
|
|
// The copy could be to an aliased physreg.
|
|
|
|
if (!lr) continue;
|
|
|
|
|
|
|
|
// DstReg is known to be a register in the LHS interval. If the src is
|
|
|
|
// from the RHS interval, we can use its value #.
|
|
|
|
if (!CP.isCoalescable(MI) &&
|
|
|
|
!RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
LHSValsDefinedFromRHS[VNI] = lr->valno;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Loop over the value numbers of the RHS, seeing if any are defined from
|
|
|
|
// the LHS.
|
|
|
|
for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
|
|
|
|
i != e; ++i) {
|
|
|
|
VNInfo *VNI = *i;
|
2012-02-04 05:20:49 +00:00
|
|
|
if (VNI->isUnused() || VNI->isPHIDef())
|
|
|
|
continue;
|
|
|
|
MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
|
|
|
|
assert(MI && "Missing def");
|
|
|
|
if (!MI->isCopyLike()) // Src not defined by a copy?
|
2012-01-27 21:43:32 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Figure out the value # from the LHS.
|
|
|
|
LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
|
|
|
|
// The copy could be to an aliased physreg.
|
|
|
|
if (!lr) continue;
|
|
|
|
|
|
|
|
// DstReg is known to be a register in the RHS interval. If the src is
|
|
|
|
// from the LHS interval, we can use its value #.
|
|
|
|
if (!CP.isCoalescable(MI) &&
|
|
|
|
!RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
RHSValsDefinedFromLHS[VNI] = lr->valno;
|
|
|
|
}
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
|
|
|
|
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
|
|
|
|
NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
|
|
|
|
|
|
|
|
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
|
|
|
|
i != e; ++i) {
|
|
|
|
VNInfo *VNI = *i;
|
|
|
|
unsigned VN = VNI->id;
|
|
|
|
if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
|
|
|
|
continue;
|
|
|
|
ComputeUltimateVN(VNI, NewVNInfo,
|
|
|
|
LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
|
|
|
|
LHSValNoAssignments, RHSValNoAssignments);
|
|
|
|
}
|
|
|
|
for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
|
|
|
|
i != e; ++i) {
|
|
|
|
VNInfo *VNI = *i;
|
|
|
|
unsigned VN = VNI->id;
|
|
|
|
if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
|
|
|
|
continue;
|
|
|
|
// If this value number isn't a copy from the LHS, it's a new number.
|
|
|
|
if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
|
|
|
|
NewVNInfo.push_back(VNI);
|
|
|
|
RHSValNoAssignments[VN] = NewVNInfo.size()-1;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
ComputeUltimateVN(VNI, NewVNInfo,
|
|
|
|
RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
|
|
|
|
RHSValNoAssignments, LHSValNoAssignments);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Armed with the mappings of LHS/RHS values to ultimate values, walk the
|
|
|
|
// interval lists to see if these intervals are coalescable.
|
|
|
|
LiveInterval::const_iterator I = LHS.begin();
|
|
|
|
LiveInterval::const_iterator IE = LHS.end();
|
|
|
|
LiveInterval::const_iterator J = RHS.begin();
|
|
|
|
LiveInterval::const_iterator JE = RHS.end();
|
|
|
|
|
|
|
|
// Skip ahead until the first place of potential sharing.
|
|
|
|
if (I != IE && J != JE) {
|
|
|
|
if (I->start < J->start) {
|
|
|
|
I = std::upper_bound(I, IE, J->start);
|
|
|
|
if (I != LHS.begin()) --I;
|
|
|
|
} else if (J->start < I->start) {
|
|
|
|
J = std::upper_bound(J, JE, I->start);
|
|
|
|
if (J != RHS.begin()) --J;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
while (I != IE && J != JE) {
|
|
|
|
// Determine if these two live ranges overlap.
|
|
|
|
bool Overlaps;
|
|
|
|
if (I->start < J->start) {
|
|
|
|
Overlaps = I->end > J->start;
|
|
|
|
} else {
|
|
|
|
Overlaps = J->end > I->start;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If so, check value # info to determine if they are really different.
|
|
|
|
if (Overlaps) {
|
|
|
|
// If the live range overlap will map to the same value number in the
|
|
|
|
// result liverange, we can still coalesce them. If not, we can't.
|
|
|
|
if (LHSValNoAssignments[I->valno->id] !=
|
|
|
|
RHSValNoAssignments[J->valno->id])
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (I->end < J->end)
|
|
|
|
++I;
|
|
|
|
else
|
|
|
|
++J;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update kill info. Some live ranges are extended due to copy coalescing.
|
|
|
|
for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
|
|
|
|
E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
|
|
|
|
VNInfo *VNI = I->first;
|
|
|
|
unsigned LHSValID = LHSValNoAssignments[VNI->id];
|
|
|
|
if (VNI->hasPHIKill())
|
|
|
|
NewVNInfo[LHSValID]->setHasPHIKill(true);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update kill info. Some live ranges are extended due to copy coalescing.
|
|
|
|
for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
|
|
|
|
E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
|
|
|
|
VNInfo *VNI = I->first;
|
|
|
|
unsigned RHSValID = RHSValNoAssignments[VNI->id];
|
|
|
|
if (VNI->hasPHIKill())
|
|
|
|
NewVNInfo[RHSValID]->setHasPHIKill(true);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (LHSValNoAssignments.empty())
|
|
|
|
LHSValNoAssignments.push_back(-1);
|
|
|
|
if (RHSValNoAssignments.empty())
|
|
|
|
RHSValNoAssignments.push_back(-1);
|
|
|
|
|
2011-07-03 05:26:42 +00:00
|
|
|
SmallVector<unsigned, 8> SourceRegisters;
|
2011-07-01 00:16:54 +00:00
|
|
|
for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
|
|
|
|
E = DupCopies.end(); I != E; ++I) {
|
|
|
|
MachineInstr *MI = *I;
|
|
|
|
|
|
|
|
// We have pretended that the assignment to B in
|
|
|
|
// A = X
|
|
|
|
// B = X
|
|
|
|
// was actually a copy from A. Now that we decided to coalesce A and B,
|
|
|
|
// transform the code into
|
|
|
|
// A = X
|
|
|
|
// X = X
|
|
|
|
// and mark the X as coalesced to keep the illusion.
|
|
|
|
unsigned Src = MI->getOperand(1).getReg();
|
2011-07-03 05:26:42 +00:00
|
|
|
SourceRegisters.push_back(Src);
|
2011-08-09 01:01:27 +00:00
|
|
|
MI->getOperand(0).substVirtReg(Src, 0, *TRI);
|
2011-07-01 00:16:54 +00:00
|
|
|
|
|
|
|
markAsJoined(MI);
|
|
|
|
}
|
|
|
|
|
2011-07-03 05:26:42 +00:00
|
|
|
// If B = X was the last use of X in a liverange, we have to shrink it now
|
|
|
|
// that B = X is gone.
|
|
|
|
for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
|
|
|
|
E = SourceRegisters.end(); I != E; ++I) {
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->shrinkToUses(&LIS->getInterval(*I));
|
2011-07-03 05:26:42 +00:00
|
|
|
}
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
// If we get here, we know that we can coalesce the live ranges. Ask the
|
|
|
|
// intervals to coalesce themselves now.
|
|
|
|
LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
|
2011-08-09 01:01:27 +00:00
|
|
|
MRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
// DepthMBBCompare - Comparison predicate that sort first based on the loop
|
|
|
|
// depth of the basic block (the unsigned), and then on the MBB number.
|
|
|
|
struct DepthMBBCompare {
|
|
|
|
typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
|
|
|
|
bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
|
|
|
|
// Deeper loops first
|
|
|
|
if (LHS.first != RHS.first)
|
|
|
|
return LHS.first > RHS.first;
|
|
|
|
|
|
|
|
// Prefer blocks that are more connected in the CFG. This takes care of
|
|
|
|
// the most difficult copies first while intervals are short.
|
|
|
|
unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
|
|
|
|
unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
|
|
|
|
if (cl != cr)
|
|
|
|
return cl > cr;
|
|
|
|
|
|
|
|
// As a last resort, sort by block number.
|
|
|
|
return LHS.second->getNumber() < RHS.second->getNumber();
|
|
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2012-05-18 21:09:40 +00:00
|
|
|
// Try joining WorkList copies starting from index From.
|
|
|
|
// Null out any successful joins.
|
|
|
|
bool RegisterCoalescer::copyCoalesceWorkList(unsigned From) {
|
|
|
|
assert(From <= WorkList.size() && "Out of range");
|
|
|
|
bool Progress = false;
|
|
|
|
for (unsigned i = From, e = WorkList.size(); i != e; ++i) {
|
|
|
|
if (!WorkList[i])
|
|
|
|
continue;
|
2012-05-19 05:25:50 +00:00
|
|
|
// Skip instruction pointers that have already been erased, for example by
|
|
|
|
// dead code elimination.
|
|
|
|
if (ErasedInstrs.erase(WorkList[i])) {
|
|
|
|
WorkList[i] = 0;
|
|
|
|
continue;
|
|
|
|
}
|
2012-05-18 21:09:40 +00:00
|
|
|
bool Again = false;
|
|
|
|
bool Success = joinCopy(WorkList[i], Again);
|
|
|
|
Progress |= Success;
|
|
|
|
if (Success || !Again)
|
|
|
|
WorkList[i] = 0;
|
|
|
|
}
|
|
|
|
return Progress;
|
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
void
|
2012-05-18 21:09:40 +00:00
|
|
|
RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
|
2011-06-26 22:06:36 +00:00
|
|
|
DEBUG(dbgs() << MBB->getName() << ":\n");
|
|
|
|
|
2012-05-18 18:21:48 +00:00
|
|
|
// Collect all copy-like instructions in MBB. Don't start coalescing anything
|
|
|
|
// yet, it might invalidate the iterator.
|
2012-05-18 21:09:40 +00:00
|
|
|
const unsigned PrevSize = WorkList.size();
|
2011-06-26 22:06:36 +00:00
|
|
|
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
|
2012-05-18 18:21:48 +00:00
|
|
|
MII != E; ++MII)
|
|
|
|
if (MII->isCopyLike())
|
2012-05-18 21:09:40 +00:00
|
|
|
WorkList.push_back(MII);
|
|
|
|
|
|
|
|
// Try coalescing the collected copies immediately, and remove the nulls.
|
|
|
|
// This prevents the WorkList from getting too large since most copies are
|
|
|
|
// joinable on the first attempt.
|
|
|
|
if (copyCoalesceWorkList(PrevSize))
|
|
|
|
WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
|
|
|
|
(MachineInstr*)0), WorkList.end());
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
2012-05-07 23:46:16 +00:00
|
|
|
void RegisterCoalescer::joinAllIntervals() {
|
2011-06-26 22:06:36 +00:00
|
|
|
DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
|
2012-05-18 21:09:40 +00:00
|
|
|
assert(WorkList.empty() && "Old data still around.");
|
2011-06-26 22:06:36 +00:00
|
|
|
|
2011-08-09 01:01:27 +00:00
|
|
|
if (Loops->empty()) {
|
2011-06-26 22:06:36 +00:00
|
|
|
// If there are no loops in the function, join intervals in function order.
|
2011-08-09 01:01:27 +00:00
|
|
|
for (MachineFunction::iterator I = MF->begin(), E = MF->end();
|
2011-06-26 22:06:36 +00:00
|
|
|
I != E; ++I)
|
2012-05-18 21:09:40 +00:00
|
|
|
copyCoalesceInMBB(I);
|
2011-06-26 22:06:36 +00:00
|
|
|
} else {
|
|
|
|
// Otherwise, join intervals in inner loops before other intervals.
|
|
|
|
// Unfortunately we can't just iterate over loop hierarchy here because
|
|
|
|
// there may be more MBB's than BB's. Collect MBB's for sorting.
|
|
|
|
|
|
|
|
// Join intervals in the function prolog first. We want to join physical
|
|
|
|
// registers with virtual registers before the intervals got too long.
|
|
|
|
std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
|
2011-08-09 01:01:27 +00:00
|
|
|
for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
|
2011-06-26 22:06:36 +00:00
|
|
|
MachineBasicBlock *MBB = I;
|
2011-08-09 01:01:27 +00:00
|
|
|
MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Sort by loop depth.
|
|
|
|
std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
|
|
|
|
|
|
|
|
// Finally, join intervals in loop nest order.
|
|
|
|
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
|
2012-05-18 21:09:40 +00:00
|
|
|
copyCoalesceInMBB(MBBs[i].second);
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Joining intervals can allow other intervals to be joined. Iteratively join
|
|
|
|
// until we make no progress.
|
2012-05-18 21:09:40 +00:00
|
|
|
while (copyCoalesceWorkList())
|
|
|
|
/* empty */ ;
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
2011-06-26 22:34:10 +00:00
|
|
|
void RegisterCoalescer::releaseMemory() {
|
2011-06-26 22:06:36 +00:00
|
|
|
JoinedCopies.clear();
|
2012-05-19 05:25:50 +00:00
|
|
|
ErasedInstrs.clear();
|
2011-06-26 22:06:36 +00:00
|
|
|
ReMatDefs.clear();
|
2012-05-18 21:09:40 +00:00
|
|
|
WorkList.clear();
|
2012-05-19 05:25:50 +00:00
|
|
|
DeadDefs.clear();
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
|
2011-06-26 22:34:10 +00:00
|
|
|
bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
|
2011-08-09 01:01:27 +00:00
|
|
|
MF = &fn;
|
|
|
|
MRI = &fn.getRegInfo();
|
|
|
|
TM = &fn.getTarget();
|
|
|
|
TRI = TM->getRegisterInfo();
|
|
|
|
TII = TM->getInstrInfo();
|
|
|
|
LIS = &getAnalysis<LiveIntervals>();
|
|
|
|
LDV = &getAnalysis<LiveDebugVariables>();
|
2011-06-26 22:06:36 +00:00
|
|
|
AA = &getAnalysis<AliasAnalysis>();
|
2011-08-09 01:01:27 +00:00
|
|
|
Loops = &getAnalysis<MachineLoopInfo>();
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
|
|
|
|
<< "********** Function: "
|
2011-08-09 01:01:27 +00:00
|
|
|
<< ((Value*)MF->getFunction())->getName() << '\n');
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
if (VerifyCoalescing)
|
2011-08-09 01:01:27 +00:00
|
|
|
MF->verify(this, "Before register coalescing");
|
2011-06-26 22:06:36 +00:00
|
|
|
|
|
|
|
RegClassInfo.runOnMachineFunction(fn);
|
|
|
|
|
|
|
|
// Join (coalesce) intervals if requested.
|
|
|
|
if (EnableJoining) {
|
2012-05-07 23:46:16 +00:00
|
|
|
joinAllIntervals();
|
2011-06-26 22:06:36 +00:00
|
|
|
DEBUG({
|
|
|
|
dbgs() << "********** INTERVALS POST JOINING **********\n";
|
2011-08-09 01:01:27 +00:00
|
|
|
for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
|
2011-06-26 22:06:36 +00:00
|
|
|
I != E; ++I){
|
2011-08-09 01:01:27 +00:00
|
|
|
I->second->print(dbgs(), TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
dbgs() << "\n";
|
|
|
|
}
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
// Perform a final pass over the instructions and compute spill weights
|
|
|
|
// and remove identity moves.
|
2011-08-09 18:19:41 +00:00
|
|
|
SmallVector<unsigned, 4> DeadDefs, InflateRegs;
|
2011-08-09 01:01:27 +00:00
|
|
|
for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
|
2011-06-26 22:06:36 +00:00
|
|
|
mbbi != mbbe; ++mbbi) {
|
|
|
|
MachineBasicBlock* mbb = mbbi;
|
|
|
|
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
|
|
|
|
mii != mie; ) {
|
|
|
|
MachineInstr *MI = mii;
|
|
|
|
if (JoinedCopies.count(MI)) {
|
|
|
|
// Delete all coalesced copies.
|
|
|
|
bool DoDelete = true;
|
|
|
|
assert(MI->isCopyLike() && "Unrecognized copy instruction");
|
|
|
|
unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
|
2011-08-09 18:19:41 +00:00
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
|
|
|
|
|
|
// Collect candidates for register class inflation.
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
|
|
|
|
RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg)))
|
|
|
|
InflateRegs.push_back(SrcReg);
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
|
|
|
|
RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg)))
|
|
|
|
InflateRegs.push_back(DstReg);
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
|
|
|
|
MI->getNumOperands() > 2)
|
|
|
|
// Do not delete extract_subreg, insert_subreg of physical
|
|
|
|
// registers unless the definition is dead. e.g.
|
|
|
|
// %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
|
|
|
|
// or else the scavenger may complain. LowerSubregs will
|
|
|
|
// delete them later.
|
|
|
|
DoDelete = false;
|
|
|
|
|
|
|
|
if (MI->allDefsAreDead()) {
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->hasInterval(SrcReg))
|
|
|
|
LIS->shrinkToUses(&LIS->getInterval(SrcReg));
|
2011-06-26 22:06:36 +00:00
|
|
|
DoDelete = true;
|
|
|
|
}
|
|
|
|
if (!DoDelete) {
|
|
|
|
// We need the instruction to adjust liveness, so make it a KILL.
|
|
|
|
if (MI->isSubregToReg()) {
|
|
|
|
MI->RemoveOperand(3);
|
|
|
|
MI->RemoveOperand(1);
|
|
|
|
}
|
2011-08-09 01:01:27 +00:00
|
|
|
MI->setDesc(TII->get(TargetOpcode::KILL));
|
2011-06-26 22:06:36 +00:00
|
|
|
mii = llvm::next(mii);
|
|
|
|
} else {
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->RemoveMachineInstrFromMaps(MI);
|
2011-06-26 22:06:36 +00:00
|
|
|
mii = mbbi->erase(mii);
|
|
|
|
++numPeep;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now check if this is a remat'ed def instruction which is now dead.
|
|
|
|
if (ReMatDefs.count(MI)) {
|
|
|
|
bool isDead = true;
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg())
|
|
|
|
continue;
|
|
|
|
unsigned Reg = MO.getReg();
|
|
|
|
if (!Reg)
|
|
|
|
continue;
|
2012-01-27 03:20:42 +00:00
|
|
|
DeadDefs.push_back(Reg);
|
2011-08-09 18:19:41 +00:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
|
|
// Remat may also enable register class inflation.
|
|
|
|
if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)))
|
|
|
|
InflateRegs.push_back(Reg);
|
|
|
|
}
|
2011-06-26 22:06:36 +00:00
|
|
|
if (MO.isDead())
|
|
|
|
continue;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
|
2011-08-09 01:01:27 +00:00
|
|
|
!MRI->use_nodbg_empty(Reg)) {
|
2011-06-26 22:06:36 +00:00
|
|
|
isDead = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (isDead) {
|
|
|
|
while (!DeadDefs.empty()) {
|
|
|
|
unsigned DeadDef = DeadDefs.back();
|
|
|
|
DeadDefs.pop_back();
|
2012-05-07 23:46:16 +00:00
|
|
|
removeDeadDef(LIS->getInterval(DeadDef), MI);
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->RemoveMachineInstrFromMaps(mii);
|
2011-06-26 22:06:36 +00:00
|
|
|
mii = mbbi->erase(mii);
|
|
|
|
continue;
|
|
|
|
} else
|
|
|
|
DeadDefs.clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
++mii;
|
|
|
|
|
|
|
|
// Check for now unnecessary kill flags.
|
2011-08-09 01:01:27 +00:00
|
|
|
if (LIS->isNotInMIMap(MI)) continue;
|
2011-11-13 20:45:27 +00:00
|
|
|
SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
|
2011-06-26 22:06:36 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (!MO.isReg() || !MO.isKill()) continue;
|
|
|
|
unsigned reg = MO.getReg();
|
2011-08-09 01:01:27 +00:00
|
|
|
if (!reg || !LIS->hasInterval(reg)) continue;
|
|
|
|
if (!LIS->getInterval(reg).killedAt(DefIdx)) {
|
2011-06-26 22:06:36 +00:00
|
|
|
MO.setIsKill(false);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// When leaving a kill flag on a physreg, check if any subregs should
|
|
|
|
// remain alive.
|
|
|
|
if (!TargetRegisterInfo::isPhysicalRegister(reg))
|
|
|
|
continue;
|
2012-03-05 05:37:41 +00:00
|
|
|
for (const uint16_t *SR = TRI->getSubRegisters(reg);
|
2011-06-26 22:06:36 +00:00
|
|
|
unsigned S = *SR; ++SR)
|
2011-08-09 01:01:27 +00:00
|
|
|
if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
|
|
|
|
MI->addRegisterDefined(S, TRI);
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-09 18:19:41 +00:00
|
|
|
// After deleting a lot of copies, register classes may be less constrained.
|
|
|
|
// Removing sub-register opreands may alow GR32_ABCD -> GR32 and DPR_VFP2 ->
|
|
|
|
// DPR inflation.
|
|
|
|
array_pod_sort(InflateRegs.begin(), InflateRegs.end());
|
|
|
|
InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
|
|
|
|
InflateRegs.end());
|
|
|
|
DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
|
|
|
|
for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
|
|
|
|
unsigned Reg = InflateRegs[i];
|
|
|
|
if (MRI->reg_nodbg_empty(Reg))
|
|
|
|
continue;
|
|
|
|
if (MRI->recomputeRegClass(Reg, *TM)) {
|
|
|
|
DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
|
|
|
|
<< MRI->getRegClass(Reg)->getName() << '\n');
|
|
|
|
++NumInflated;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-26 22:06:36 +00:00
|
|
|
DEBUG(dump());
|
2011-08-09 01:01:27 +00:00
|
|
|
DEBUG(LDV->dump());
|
2011-06-26 22:06:36 +00:00
|
|
|
if (VerifyCoalescing)
|
2011-08-09 01:01:27 +00:00
|
|
|
MF->verify(this, "After register coalescing");
|
2011-06-26 22:06:36 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// print - Implement the dump method.
|
2011-06-26 22:34:10 +00:00
|
|
|
void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {
|
2011-08-09 01:01:27 +00:00
|
|
|
LIS->print(O, m);
|
2011-06-26 22:06:36 +00:00
|
|
|
}
|