llvm-6502/test/MC/Mips/mips2/invalid-mips32r2-xfail.s

# Instructions that are supposed to be invalid but currently aren't
# This test will XPASS if any insn stops assembling.
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
# RUN:     2> %t1
# RUN: not FileCheck %s < %t1
# XFAIL: *

# CHECK-NOT: error
        .set noat
        rdhwr   $sp,$11
[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2\|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8 2014-05-13 11:45:36 +00:00			`# Instructions that are supposed to be invalid but currently aren't`
			`# This test will XPASS if any insn stops assembling.`
			`#`
			`# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \`
			`# RUN: 2> %t1`
			`# RUN: not FileCheck %s < %t1`
			`# XFAIL: *`

			`# CHECK-NOT: error`
			`.set noat`
			`rdhwr $sp,$11`