llvm-6502/test/CodeGen/X86/fp-stack-compare.ll

; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s
; PR6679

define float @foo(float* %col.2.0) {
; CHECK: fucomp
; CHECK-NOT: fucompi
; CHECK: j
; CHECK-NOT: fcmov
  %tmp = load float* %col.2.0
  %tmp16 = fcmp olt float %tmp, 0.000000e+00
  %tmp20 = fsub float -0.000000e+00, %tmp
  %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
  ret float %iftmp.2.0
}
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-14 01:11:51 +00:00			`; RUN: llc < %s -march=x86 -mcpu=i386 \| FileCheck %s`
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM, FNSTSW and SAHF instructions. During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8 2012-04-27 12:07:43 +00:00			`; PR6679`
Testcase for pr1012 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31875 91177308-0d34-0410-b5e6-96231b3b80d8 2006-11-20 17:55:30 +00:00
Remove llvm-upgrade and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47432 91177308-0d34-0410-b5e6-96231b3b80d8 2008-02-21 07:42:26 +00:00			`define float @foo(float* %col.2.0) {`
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM, FNSTSW and SAHF instructions. During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8 2012-04-27 12:07:43 +00:00			`; CHECK: fucomp`
			`; CHECK-NOT: fucompi`
			`; CHECK: j`
			`; CHECK-NOT: fcmov`
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8 2011-04-14 01:11:51 +00:00			`%tmp = load float* %col.2.0`
			`%tmp16 = fcmp olt float %tmp, 0.000000e+00`
			`%tmp20 = fsub float -0.000000e+00, %tmp`
			`%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp`
			`ret float %iftmp.2.0`
Testcase for pr1012 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31875 91177308-0d34-0410-b5e6-96231b3b80d8 2006-11-20 17:55:30 +00:00			`}`