llvm-6502/test/CodeGen/Thumb/barrier.ll

; RUN: llc < %s -mtriple=thumbv6-apple-darwin  | FileCheck %s -check-prefix=V6
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6
; RUN: llc < %s -march=thumb -mcpu=cortex-m0   | FileCheck %s -check-prefix=V6M

define void @t1() {
; V6: t1:
; V6: blx {{_*}}sync_synchronize

; V6M: t1:
; V6M: dmb ish
  fence seq_cst
  ret void
}
Fix test and re-enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 17:25:51 +00:00			`; RUN: llc < %s -mtriple=thumbv6-apple-darwin \| FileCheck %s -check-prefix=V6`
Do not use MEMBARRIER_MCR for any Thumb code. It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8 2010-11-09 22:50:44 +00:00			`; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db \| FileCheck %s -check-prefix=V6`
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8 2011-07-07 03:55:05 +00:00			`; RUN: llc < %s -march=thumb -mcpu=cortex-m0 \| FileCheck %s -check-prefix=V6M`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:22:01 +00:00
			`define void @t1() {`
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit instructions: dmb, dsb, isb, msr, and mrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:30:38 +00:00			`; V6: t1:`
Fix test and re-enable it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 17:25:51 +00:00			`; V6: blx {{_*}}sync_synchronize`
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit instructions: dmb, dsb, isb, msr, and mrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:30:38 +00:00
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:51:54 +00:00			`; V6M: t1:`
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-30 00:54:37 +00:00			`; V6M: dmb ish`
Convert more tests to new atomic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140567 91177308-0d34-0410-b5e6-96231b3b80d8 2011-09-26 21:36:10 +00:00			`fence seq_cst`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:22:01 +00:00			`ret void`
			`}`