2012-08-22 02:51:28 +00:00
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; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | \
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; RUN: FileCheck %s -check-prefix=PIC
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; RUN: llc -march=mipsel -relocation-model=static -disable-mips-delay-filler < \
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; RUN: %s | FileCheck %s -check-prefix=STATIC
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; RUN: llc -march=mipsel -relocation-model=static -disable-mips-delay-filler \
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; RUN: -mips-fix-global-base-reg=false < %s | \
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; RUN: FileCheck %s -check-prefix=STATICGP
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2011-05-31 02:53:58 +00:00
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@t1 = thread_local global i32 0, align 4
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define i32 @f1() nounwind {
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entry:
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%tmp = load i32* @t1, align 4
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ret i32 %tmp
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; CHECK: f1:
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2012-05-12 03:25:16 +00:00
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; PIC: addu $[[R0:[a-z0-9]+]], $2, $25
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; PIC: lw $25, %call16(__tls_get_addr)($[[R0]])
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; PIC: addiu $4, $[[R0]], %tlsgd(t1)
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2011-05-31 02:53:58 +00:00
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; PIC: jalr $25
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; PIC: lw $2, 0($2)
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; STATIC: rdhwr $3, $29
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; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
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; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
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; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]]
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; STATIC: lw $2, 0($[[R2]])
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}
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@t2 = external thread_local global i32
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define i32 @f2() nounwind {
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entry:
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%tmp = load i32* @t2, align 4
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ret i32 %tmp
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; CHECK: f2:
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2012-05-12 03:25:16 +00:00
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; PIC: addu $[[R0:[a-z0-9]+]], $2, $25
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; PIC: lw $25, %call16(__tls_get_addr)($[[R0]])
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; PIC: addiu $4, $[[R0]], %tlsgd(t2)
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2011-05-31 02:53:58 +00:00
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; PIC: jalr $25
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; PIC: lw $2, 0($2)
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2012-02-24 22:34:47 +00:00
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; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
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; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
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; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]])
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2012-05-12 00:17:17 +00:00
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; STATIC: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
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2012-05-12 03:25:16 +00:00
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; STATIC: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
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2011-05-31 02:53:58 +00:00
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; STATIC: rdhwr $3, $29
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2012-05-12 03:25:16 +00:00
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; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
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2011-05-31 02:53:58 +00:00
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; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]]
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; STATIC: lw $2, 0($[[R1]])
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}
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2011-12-14 18:26:41 +00:00
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@f3.i = internal thread_local unnamed_addr global i32 1, align 4
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define i32 @f3() nounwind {
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entry:
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; CHECK: f3:
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2012-05-12 03:25:16 +00:00
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; PIC: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
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2011-12-14 18:26:41 +00:00
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; PIC: jalr $25
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; PIC: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
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; PIC: addu $[[R1:[0-9]+]], $[[R0]], $2
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Remove the restriction on the first operand of the add node in SelectAddr.
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:28:37 +00:00
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; PIC: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
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2011-12-14 18:26:41 +00:00
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%0 = load i32* @f3.i, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @f3.i, align 4
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ret i32 %inc
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}
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