2005-08-18 18:45:24 +00:00
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//===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple code linearizer for DAGs. This is not a very good
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// way to emit code, but gets working code quickly.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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2005-08-19 20:45:43 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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2005-08-18 18:45:24 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2005-08-18 20:07:59 +00:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2005-08-19 20:45:43 +00:00
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#include "llvm/CodeGen/SSARegMap.h"
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2005-08-18 20:07:59 +00:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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2005-08-18 20:11:49 +00:00
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#include "llvm/Support/CommandLine.h"
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2005-08-18 18:45:24 +00:00
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using namespace llvm;
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2005-08-18 20:11:49 +00:00
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#ifndef _NDEBUG
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static cl::opt<bool>
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ViewDAGs("view-sched-dags", cl::Hidden,
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cl::desc("Pop up a window to show sched dags as they are processed"));
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#else
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static const bool ViewDAGS = 0;
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#endif
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2005-08-18 20:07:59 +00:00
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namespace {
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class SimpleSched {
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SelectionDAG &DAG;
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MachineBasicBlock *BB;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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2005-08-19 20:50:53 +00:00
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const MRegisterInfo &MRI;
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2005-08-19 20:45:43 +00:00
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SSARegMap *RegMap;
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2005-08-18 20:07:59 +00:00
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std::map<SDNode *, unsigned> EmittedOps;
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public:
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SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
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2005-08-19 20:45:43 +00:00
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: DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
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2005-08-19 20:50:53 +00:00
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MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()) {
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2005-08-18 20:07:59 +00:00
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assert(&TII && "Target doesn't provide instr info?");
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2005-08-19 20:50:53 +00:00
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assert(&MRI && "Target doesn't provide register info?");
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2005-08-18 20:07:59 +00:00
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}
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void Run() {
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Emit(DAG.getRoot());
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}
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private:
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unsigned Emit(SDOperand Op);
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};
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}
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unsigned SimpleSched::Emit(SDOperand Op) {
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// Check to see if we have already emitted this. If so, return the value
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// already emitted. Note that if a node has a single use it cannot be
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// revisited, so don't bother putting it in the map.
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unsigned *OpSlot;
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if (Op.Val->hasOneUse()) {
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OpSlot = 0; // No reuse possible.
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} else {
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std::map<SDNode *, unsigned>::iterator OpI = EmittedOps.lower_bound(Op.Val);
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if (OpI != EmittedOps.end() && OpI->first == Op.Val)
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return OpI->second + Op.ResNo;
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OpSlot = &EmittedOps.insert(OpI, std::make_pair(Op.Val, 0))->second;
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}
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unsigned ResultReg = 0;
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if (Op.isTargetOpcode()) {
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unsigned Opc = Op.getTargetOpcode();
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const TargetInstrDescriptor &II = TII.get(Opc);
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// Target nodes have any register or immediate operands before any chain
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// nodes. Check that the DAG matches the TD files's expectation of #
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// operands.
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2005-08-19 20:45:43 +00:00
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unsigned NumResults = Op.Val->getNumValues();
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2005-08-21 18:49:29 +00:00
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if (NumResults && Op.Val->getValueType(NumResults-1) == MVT::Other)
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2005-08-19 20:45:43 +00:00
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--NumResults;
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2005-08-24 22:02:41 +00:00
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unsigned NodeOperands = Op.getNumOperands();
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if (NodeOperands && // Ignore chain if it exists.
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Op.getOperand(NodeOperands-1).getValueType() == MVT::Other)
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--NodeOperands;
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unsigned NumMIOperands = NodeOperands+NumResults;
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2005-08-19 01:01:34 +00:00
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#ifndef _NDEBUG
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2005-08-24 22:02:41 +00:00
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assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
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2005-08-18 20:07:59 +00:00
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"#operands for dag node doesn't match .td file!");
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2005-08-19 01:01:34 +00:00
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#endif
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2005-08-18 20:07:59 +00:00
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// Create the new machine instruction.
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2005-08-24 22:02:41 +00:00
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MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
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2005-08-18 20:07:59 +00:00
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// Add result register values for things that are defined by this
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// instruction.
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2005-08-19 20:45:43 +00:00
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if (NumResults) {
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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const TargetOperandInfo *OpInfo = II.OpInfo;
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ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
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MI->addRegOperand(ResultReg, MachineOperand::Def);
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for (unsigned i = 1; i != NumResults; ++i) {
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assert(OpInfo[i].RegClass && "Isn't a register operand!");
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MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
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MachineOperand::Def);
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}
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}
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2005-08-18 20:07:59 +00:00
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// Emit all of the operands of this instruction, adding them to the
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// instruction as appropriate.
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for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
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2005-08-22 01:04:32 +00:00
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if (Op.getOperand(i).isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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unsigned R = Emit(Op.getOperand(i));
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// Add an operand, unless this corresponds to a chain node.
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if (Op.getOperand(i).getValueType() != MVT::Other)
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MI->addRegOperand(R, MachineOperand::Use);
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
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2005-08-18 20:07:59 +00:00
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MI->addZeroExtImm64Operand(C->getValue());
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} else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
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MI->addRegOperand(R->getReg(), MachineOperand::Use);
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2005-08-19 22:38:24 +00:00
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} else if (GlobalAddressSDNode *TGA =
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dyn_cast<GlobalAddressSDNode>(Op.getOperand(i))) {
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MI->addGlobalAddressOperand(TGA->getGlobal(), false, 0);
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2005-08-21 18:49:29 +00:00
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} else if (BasicBlockSDNode *BB =
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dyn_cast<BasicBlockSDNode>(Op.getOperand(i))) {
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MI->addMachineBasicBlockOperand(BB->getBasicBlock());
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2005-08-21 19:56:04 +00:00
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} else if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Op.getOperand(i))) {
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MI->addFrameIndexOperand(FI->getIndex());
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2005-08-22 01:04:32 +00:00
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Op.getOperand(i))) {
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MI->addConstantPoolIndexOperand(CP->getIndex());
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2005-08-24 22:02:41 +00:00
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} else if (ExternalSymbolSDNode *ES =
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dyn_cast<ExternalSymbolSDNode>(Op.getOperand(i))) {
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MI->addExternalSymbolOperand(ES->getSymbol(), false);
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2005-08-18 20:07:59 +00:00
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} else {
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unsigned R = Emit(Op.getOperand(i));
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// Add an operand, unless this corresponds to a chain node.
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if (Op.getOperand(i).getValueType() != MVT::Other)
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MI->addRegOperand(R, MachineOperand::Use);
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}
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}
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// Now that we have emitted all operands, emit this instruction itself.
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BB->insert(BB->end(), MI);
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} else {
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switch (Op.getOpcode()) {
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2005-08-19 01:01:34 +00:00
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default:
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Op.Val->dump();
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assert(0 && "This target-independent node should have been selected!");
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2005-08-21 19:56:04 +00:00
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case ISD::EntryToken: break;
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Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg. This allows
us to compile stuff like this:
double %test(double %A, double %B, double %C, double %E) {
%F = mul double %A, %A
%G = add double %F, %B
%H = sub double -0.0, %G
%I = mul double %H, %C
%J = add double %I, %E
ret double %J
}
to:
_test:
fnmadd f0, f1, f1, f2
fmadd f1, f0, f3, f4
blr
woot!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22937 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 21:43:53 +00:00
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case ISD::TokenFactor:
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for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
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Emit(Op.getOperand(i));
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break;
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2005-08-19 01:01:34 +00:00
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case ISD::CopyToReg: {
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Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg. This allows
us to compile stuff like this:
double %test(double %A, double %B, double %C, double %E) {
%F = mul double %A, %A
%G = add double %F, %B
%H = sub double -0.0, %G
%I = mul double %H, %C
%J = add double %I, %E
ret double %J
}
to:
_test:
fnmadd f0, f1, f1, f2
fmadd f1, f0, f3, f4
blr
woot!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22937 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 21:43:53 +00:00
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Emit(Op.getOperand(0)); // Emit the chain.
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2005-08-19 01:01:34 +00:00
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unsigned Val = Emit(Op.getOperand(2));
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2005-08-19 20:50:53 +00:00
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MRI.copyRegToReg(*BB, BB->end(),
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cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
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RegMap->getRegClass(Val));
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2005-08-19 01:01:34 +00:00
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break;
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}
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Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg. This allows
us to compile stuff like this:
double %test(double %A, double %B, double %C, double %E) {
%F = mul double %A, %A
%G = add double %F, %B
%H = sub double -0.0, %G
%I = mul double %H, %C
%J = add double %I, %E
ret double %J
}
to:
_test:
fnmadd f0, f1, f1, f2
fmadd f1, f0, f3, f4
blr
woot!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22937 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 21:43:53 +00:00
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case ISD::CopyFromReg: {
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Emit(Op.getOperand(0)); // Emit the chain.
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unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
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// Figure out the register class to create for the destreg.
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2005-08-20 18:07:27 +00:00
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const TargetRegisterClass *TRC = 0;
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Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg. This allows
us to compile stuff like this:
double %test(double %A, double %B, double %C, double %E) {
%F = mul double %A, %A
%G = add double %F, %B
%H = sub double -0.0, %G
%I = mul double %H, %C
%J = add double %I, %E
ret double %J
}
to:
_test:
fnmadd f0, f1, f1, f2
fmadd f1, f0, f3, f4
blr
woot!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22937 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 21:43:53 +00:00
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if (MRegisterInfo::isVirtualRegister(SrcReg)) {
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TRC = RegMap->getRegClass(SrcReg);
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} else {
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// FIXME: we don't know what register class to generate this for. Do
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// a brute force search and pick the first match. :(
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for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
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E = MRI.regclass_end(); I != E; ++I)
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if ((*I)->contains(SrcReg)) {
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TRC = *I;
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break;
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}
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assert(TRC && "Couldn't find register class for reg copy!");
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}
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// Create the reg, emit the copy.
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ResultReg = RegMap->createVirtualRegister(TRC);
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MRI.copyRegToReg(*BB, BB->end(), ResultReg, SrcReg, TRC);
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break;
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}
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2005-08-18 20:07:59 +00:00
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}
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}
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if (OpSlot) *OpSlot = ResultReg;
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return ResultReg+Op.ResNo;
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}
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2005-08-18 18:45:24 +00:00
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
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2005-08-18 20:11:49 +00:00
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if (ViewDAGs) SD.viewGraph();
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2005-08-18 20:07:59 +00:00
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SimpleSched(SD, BB).Run();
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2005-08-18 18:45:24 +00:00
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}
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