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https://github.com/c64scene-ar/llvm-6502.git
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75 lines
1.6 KiB
LLVM
75 lines
1.6 KiB
LLVM
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; RUN: llc < %s -mtriple=armv7 -mattr=+db | FileCheck %s
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@x1 = global i32 0, align 4
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@x2 = global i32 0, align 4
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define void @test() {
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.013 = phi i32 [ 1, %entry ], [ %inc6, %for.body ]
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store atomic i32 %i.013, i32* @x1 seq_cst, align 4
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store atomic i32 %i.013, i32* @x1 seq_cst, align 4
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store atomic i32 %i.013, i32* @x2 seq_cst, align 4
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%inc6 = add nsw i32 %i.013, 1
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%exitcond = icmp eq i32 %inc6, 2
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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; The for.body contains 3 seq_cst stores.
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; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
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; CHECK: %for.body
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; CHECK-NOT: str
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; CHECK: dmb
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; CHECK-NOT: dmb
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; CHECK: str
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; CHECK-NOT: str
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; CHECK: dmb
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; CHECK-NOT: dmb
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; CHECK: str
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; CHECK-NOT: str
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; CHECK: dmb
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; CHECK-NOT: dmb
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; CHECK: str
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; CHECK-NOT: str
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; CHECK: dmb
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; CHECK-NOT: dmb
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; CHECK-NOT: str
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; CHECK: %for.end
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}
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define void @test2() {
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call void @llvm.arm.dmb(i32 11)
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tail call void @test()
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call void @llvm.arm.dmb(i32 11)
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ret void
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; the call should prevent the two dmbs from collapsing
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; CHECK: test2:
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; CHECK: dmb
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; CHECK-NEXT: bl
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; CHECK-NEXT: dmb
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}
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define void @test3() {
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call void @llvm.arm.dmb(i32 11)
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call void @llvm.arm.dsb(i32 9)
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call void @llvm.arm.dmb(i32 11)
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ret void
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; the call should prevent the two dmbs from collapsing
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; CHECK: test3:
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; CHECK: dmb
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; CHECK-NEXT: dsb
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; CHECK-NEXT: dmb
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}
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declare void @llvm.arm.dmb(i32)
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declare void @llvm.arm.dsb(i32)
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