Simon Pilgrim 3f1d66fe93 [X86][SSE] Vector integer to float conversion memory folding ... Added missing memory folding for the (V)CVTDQ2PS instructions - we can safely fold these (but not the (V)CVTDQ2PD versions which have a register/memory size discrepancy in the source operand). I've added a test case demonstrating that stack folding now works. Differential Revision: http://reviews.llvm.org/D5981 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221407 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-05 22:28:25 +00:00
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AArch64
ARM
CPP
Generic
Hexagon
Inputs
Mips	ps][microMIPS] Implement CodeGen support for ANDI16 instruction	2014-11-05 17:43:00 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC
R600	R600/SI: Add testcase I forgot to commit from months ago	2014-11-05 19:01:22 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[X86][SSE] Vector integer to float conversion memory folding	2014-11-05 22:28:25 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00