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https://github.com/c64scene-ar/llvm-6502.git
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49 lines
1.2 KiB
LLVM
49 lines
1.2 KiB
LLVM
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; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
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define <4 x i32> @test1(<4 x i32>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
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%v0 = load <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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; CHECK-LABEL: @test1
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; CHECK: li [[REG:[0-9]+]], 16
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; CHECK-NOT: li {{[0-9]+}}, 15
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; CHECK-DAG: lvx {{[0-9]+}}, 0, 3
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; CHECK-DAG: lvx {{[0-9]+}}, 3, [[REG]]
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; CHECK: blr
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}
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declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*) #0
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define <4 x i32> @test2(<4 x i32>* %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2
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; CHECK: li [[REG:[0-9]+]], 16
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; CHECK-NOT: li {{[0-9]+}}, 15
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; CHECK-DAG: lvx {{[0-9]+}}, 0, 3
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; CHECK-DAG: lvx {{[0-9]+}}, 3, [[REG]]
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; CHECK: blr
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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