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llvm-6502/test/CodeGen/Mips/msa/shift-dagcombine.ll

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Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 17:23:41 +00:00
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @ashr_v4i32(<4 x i32>* %c) nounwind {
; CHECK-LABEL: ashr_v4i32:
%1 = ashr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sra
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
; CHECK-NOT: sra
store volatile <4 x i32> %1, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
%2 = ashr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sra
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -2
; CHECK-NOT: sra
store volatile <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
ret void
; CHECK-LABEL: .size ashr_v4i32
}
define void @lshr_v4i32(<4 x i32>* %c) nounwind {
; CHECK-LABEL: lshr_v4i32:
%1 = lshr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: srl
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
; CHECK-NOT: srl
store volatile <4 x i32> %1, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
%2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: srl
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]])
Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 17:23:41 +00:00
; CHECK-NOT: srl
store volatile <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
ret void
; CHECK-LABEL: .size lshr_v4i32
}
define void @shl_v4i32(<4 x i32>* %c) nounwind {
; CHECK-LABEL: shl_v4i32:
%1 = shl <4 x i32> <i32 8, i32 4, i32 2, i32 1>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sll
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 8
; CHECK-NOT: sll
store volatile <4 x i32> %1, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
%2 = shl <4 x i32> <i32 -8, i32 -4, i32 -2, i32 -1>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sll
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -8
; CHECK-NOT: sll
store volatile <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
ret void
; CHECK-LABEL: .size shl_v4i32
}
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