mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 03:30:28 +00:00
fc210ac1ef
Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.0 KiB
LLVM
72 lines
2.0 KiB
LLVM
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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define void @ashr_v4i32(<4 x i32>* %c) nounwind {
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; CHECK-LABEL: ashr_v4i32:
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%1 = ashr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
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<i32 0, i32 1, i32 2, i32 3>
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; CHECK-NOT: sra
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; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
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; CHECK-NOT: sra
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store volatile <4 x i32> %1, <4 x i32>* %c
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; CHECK-DAG: st.w [[R1]], 0($4)
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%2 = ashr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
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<i32 0, i32 1, i32 2, i32 3>
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; CHECK-NOT: sra
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; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -2
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; CHECK-NOT: sra
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store volatile <4 x i32> %2, <4 x i32>* %c
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; CHECK-DAG: st.w [[R1]], 0($4)
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ret void
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; CHECK-LABEL: .size ashr_v4i32
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}
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define void @lshr_v4i32(<4 x i32>* %c) nounwind {
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; CHECK-LABEL: lshr_v4i32:
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%1 = lshr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
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<i32 0, i32 1, i32 2, i32 3>
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; CHECK-NOT: srl
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; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
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; CHECK-NOT: srl
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store volatile <4 x i32> %1, <4 x i32>* %c
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; CHECK-DAG: st.w [[R1]], 0($4)
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%2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
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<i32 0, i32 1, i32 2, i32 3>
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; CHECK-NOT: srl
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; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]])
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; CHECK-NOT: srl
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store volatile <4 x i32> %2, <4 x i32>* %c
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; CHECK-DAG: st.w [[R1]], 0($4)
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ret void
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; CHECK-LABEL: .size lshr_v4i32
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}
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define void @shl_v4i32(<4 x i32>* %c) nounwind {
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; CHECK-LABEL: shl_v4i32:
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%1 = shl <4 x i32> <i32 8, i32 4, i32 2, i32 1>,
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<i32 0, i32 1, i32 2, i32 3>
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; CHECK-NOT: sll
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; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 8
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; CHECK-NOT: sll
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store volatile <4 x i32> %1, <4 x i32>* %c
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; CHECK-DAG: st.w [[R1]], 0($4)
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%2 = shl <4 x i32> <i32 -8, i32 -4, i32 -2, i32 -1>,
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<i32 0, i32 1, i32 2, i32 3>
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; CHECK-NOT: sll
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; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -8
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; CHECK-NOT: sll
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store volatile <4 x i32> %2, <4 x i32>* %c
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; CHECK-DAG: st.w [[R1]], 0($4)
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ret void
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; CHECK-LABEL: .size shl_v4i32
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}
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