2009-11-07 22:00:39 +00:00
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//===- Thumb1RegisterInfo.h - Thumb-1 Register Information Impl -*- C++ -*-===//
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2009-06-27 12:16:40 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2009-11-07 22:00:39 +00:00
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// This file contains the Thumb-1 implementation of the TargetRegisterInfo
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// class.
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2009-06-27 12:16:40 +00:00
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//
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//===----------------------------------------------------------------------===//
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2009-07-02 22:18:33 +00:00
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#ifndef THUMB1REGISTERINFO_H
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#define THUMB1REGISTERINFO_H
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2009-06-27 12:16:40 +00:00
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#include "ARM.h"
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2012-03-17 07:33:42 +00:00
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#include "ARMBaseRegisterInfo.h"
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2009-06-27 12:16:40 +00:00
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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2009-07-08 18:31:39 +00:00
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class ARMBaseInstrInfo;
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2009-06-27 12:16:40 +00:00
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2009-07-02 22:18:33 +00:00
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struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
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2009-06-27 12:16:40 +00:00
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public:
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2009-07-08 18:31:39 +00:00
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Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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2009-06-27 12:16:40 +00:00
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2011-04-26 18:52:33 +00:00
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const TargetRegisterClass*
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getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
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2012-05-07 22:10:26 +00:00
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const TargetRegisterClass*
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getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
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2011-03-31 23:02:15 +00:00
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2009-06-27 12:16:40 +00:00
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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2009-07-08 18:31:39 +00:00
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void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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2009-07-08 20:28:28 +00:00
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DebugLoc dl,
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2009-07-16 09:20:10 +00:00
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unsigned DestReg, unsigned SubIdx, int Val,
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2009-07-08 18:31:39 +00:00
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ARMCC::CondCodes Pred = ARMCC::AL,
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2011-03-05 18:43:50 +00:00
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unsigned PredReg = 0,
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unsigned MIFlags = MachineInstr::NoFlags) const;
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2009-06-27 12:16:40 +00:00
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2010-08-19 17:52:13 +00:00
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// rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
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// however much remains to be handled. Return 'true' if no further
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// work is required.
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bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) const;
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void resolveFrameIndex(MachineBasicBlock::iterator I,
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unsigned BaseReg, int64_t Offset) const;
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2009-10-05 22:30:23 +00:00
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bool saveScavengerRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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2009-10-19 22:27:30 +00:00
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MachineBasicBlock::iterator &UseMI,
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2009-10-05 22:30:23 +00:00
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const TargetRegisterClass *RC,
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unsigned Reg) const;
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2010-08-26 23:32:16 +00:00
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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2013-01-31 20:02:54 +00:00
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = NULL) const;
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2009-06-27 12:16:40 +00:00
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};
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}
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2009-07-02 22:18:33 +00:00
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#endif // THUMB1REGISTERINFO_H
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